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43 lines
1.4 KiB
Verilog
43 lines
1.4 KiB
Verilog
//============================================================================
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// SNK Alpha68k for MiSTer
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//
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// Copyright (C) 2020 Sean 'Furrtek' Gonsalves
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module C74669 (
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input [2:0] IN,
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input E1, nE2, nE3,
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output reg [7:0] OUT
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);
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always @(*)
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begin
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case ({E1, E2, E3, IN)
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6'b100000: OUT <= 8'b11111110;
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6'b100001: OUT <= 8'b11111101;
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6'b100010: OUT <= 8'b11111011;
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6'b100011: OUT <= 8'b11110111;
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6'b100100: OUT <= 8'b11101111;
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6'b100101: OUT <= 8'b11011111;
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6'b100110: OUT <= 8'b10111111;
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6'b100111: OUT <= 8'b01111111;
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default: OUT <= 8'b11111111;
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endcase
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end
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endmodule
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