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41 lines
1.2 KiB
Verilog
41 lines
1.2 KiB
Verilog
//============================================================================
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// SNK Alpha68k for MiSTer
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//
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// Copyright (C) 2020 Sean 'Furrtek' Gonsalves
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module C74669 (
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input [3:0] DIN,
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input CLK,
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input DU,
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input nLOAD,
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output reg [3:0] QOUT,
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output RCO
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);
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assign RCO = DU ? (QOUT == 4'd0) : (QOUT == 4'd15);
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always @(posedge CLK or negedge nLOAD)
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begin
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if (!nLOAD)
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QOUT <= DIN;
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else
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QOUT <= DU ? QOUT - 4'd1 : QOUT + 4'd1;
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end
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endmodule
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