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42 lines
1.2 KiB
Verilog
42 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 20:13:54 04/24/2018
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// Design Name: LS153
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// Module Name: system86/ttl/ls153.v
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// Project Name: Namco System86 simulation
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// Target Devices:
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// Tool versions:
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// Description: LS153 - Dual 4-Line To 1-Line Data Selectors/Multiplexers
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LS153(
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input wire S0,
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input wire S1,
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input wire Ea,
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input wire I0a,
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input wire I1a,
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input wire I2a,
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input wire I3a,
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input wire Eb,
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input wire I0b,
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input wire I1b,
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input wire I2b,
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input wire I3b,
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output wire Za,
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output wire Zb
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);
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assign Za = Ea & ((I0a & ~S1 & ~S0) | (I1a & ~S1 & S0) | (I2a & S1 & ~S0) | (I3a & S1 & S0));
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assign Zb = Eb & ((I0b & ~S1 & ~S0) | (I1b & ~S1 & S0) | (I2b & S1 & ~S0) | (I3b & S1 & S0));
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endmodule
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