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33 lines
855 B
Verilog
33 lines
855 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 21:46:13 05/04/2018
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// Design Name: LS158
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// Module Name: system86/ttl/ls158.v
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// Project Name: Namco System86 simulation
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// Target Devices:
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// Tool versions:
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// Description: LS158 - As LS157 only with inverted outputs
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LS158(
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input wire G,
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input wire SELA,
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input wire [3:0] A,
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input wire [3:0] B,
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output wire [3:0] Y
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);
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assign Y = G ? ~(SELA ? A : B) : 4'b1;
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endmodule
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