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37 lines
817 B
Verilog
37 lines
817 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 21:51:32 05/14/2018
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// Design Name: LS273
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// Module Name: system86/ttl/ls273.v
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// Project Name: Namco System86 simulation
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LS273(
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input wire CLK,
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input wire CLR,
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input wire [7:0] D,
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output reg [7:0] Q
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);
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always @(posedge CLK) begin
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if (CLR)
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Q = 8'b0;
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else
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Q = D;
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end
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endmodule
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