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67 lines
1.4 KiB
Verilog
67 lines
1.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 19:24:54 05/16/2018
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// Design Name: LS47
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// Module Name: system86/ttl/ls74.v
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// Project Name: Namco System86 simulation
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// Target Devices:
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// Tool versions:
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// Description: LS74 - Dual D-Type Positive-Edge -Triggered Flip-Flops With Preset and Clear
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LS74(
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input wire CLR1,
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input wire CLR2,
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input wire CLK1,
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input wire CLK2,
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input wire PRE1,
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input wire PRE2,
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input wire D1,
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input wire D2,
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output reg Q1,
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output reg Q2,
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output reg nQ1,
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output reg nQ2
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);
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reg Q1Next = 0;
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reg Q2Next = 0;
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always @(posedge CLK1) begin
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Q1Next <= D1;
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end
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always @(posedge CLK2) begin
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Q2Next <= D2;
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end
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always @(PRE1 or CLR1 or Q1Next) begin
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if (!PRE1 && !CLR1) begin
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Q1 <= Q1Next;
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end else begin
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Q1 <= PRE1;
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nQ1 <= PRE1 || !CLR1;
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end
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end
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always @(PRE2 or CLR2 or Q2Next) begin
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if (!PRE2 && !CLR2) begin
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Q2 <= Q2Next;
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end else begin
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Q2 <= PRE2;
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nQ2 <= PRE2 || !CLR2;
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end
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end
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endmodule
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