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38 lines
1.0 KiB
Verilog
38 lines
1.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 22:06:05 05/14/2018
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// Design Name: LS85
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// Module Name: system86/ttl/ls85.v
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// Project Name: Namco System86 simulation
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// Target Devices:
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// Tool versions:
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// Description: LS85 - 4-Bit Magnitude Comparators
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LS85(
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input wire [3:0] A,
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input wire [3:0] B,
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output wire AgtBin,
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output wire AeqBin,
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output wire AltBin,
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output wire AgtBout,
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output wire AeqBout,
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output wire AltBout
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);
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assign AgtBout = (A > B) || (!AeqBin && AgtBin && (A == B));
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assign AeqBout = (A == B) && AeqBin;
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assign AltBout = (A < B) || (!AeqBin && AltBin && (A == B));
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endmodule
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