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https://github.com/Gehstock/Mist_FPGA.git
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244 lines
8.1 KiB
VHDL
244 lines
8.1 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- FPGA Lady Bug
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--
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-- Toplevel port for Papilio Plus board.
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--
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-------------------------------------------------------------------------------
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library ieee;
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use ieee.numeric_std.all;
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use work.ladybug_dip_pack.all;
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entity ladybugt is
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port (
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-- Global Interface -------------------------------------------------------
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CLK_IN : in std_logic; -- 20MHz
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I_RESET : in std_logic;
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-- VGA Interface ----------------------------------------------------------
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O_VIDEO_R : out std_logic_vector( 1 downto 0);
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O_VIDEO_G : out std_logic_vector( 1 downto 0);
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O_VIDEO_B : out std_logic_vector( 1 downto 0);
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O_VSYNC : out std_logic;
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O_HSYNC : out std_logic;
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O_VBLANK : out std_logic;
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O_HBLANK : out std_logic;
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O_PIXCE : out std_logic;
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-- Audio Interface --------------------------------------------------------
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O_AUDIO : out signed(7 downto 0);
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but_coin_s : in std_logic_vector( 1 downto 0);
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but_fire_s : in std_logic_vector( 1 downto 0);
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but_bomb_s : in std_logic_vector( 1 downto 0);
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but_tilt_s : in std_logic_vector( 1 downto 0);
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but_select_s : in std_logic_vector( 1 downto 0);
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but_up_s : in std_logic_vector( 1 downto 0);
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but_down_s : in std_logic_vector( 1 downto 0);
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but_left_s : in std_logic_vector( 1 downto 0);
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but_right_s : in std_logic_vector( 1 downto 0)
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);
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end ladybugt;
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architecture struct of ladybugt is
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signal
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ps2_codeready,
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clk_20mhz_s,
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clk_en_5mhz_s,
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ext_res_n_s,
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ext_res_s,
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audio_s,
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vid_hsync,
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vid_vsync,
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vga_hsync,
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vid_comp_sync_n,
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vga_vsync : std_logic;
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signal rom_cpu_a_s : std_logic_vector(14 downto 0);
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signal rom_cpu_d_s : std_logic_vector( 7 downto 0);
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signal rom_cpu_d1 : std_logic_vector( 7 downto 0);
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signal rom_cpu_d2 : std_logic_vector( 7 downto 0);
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signal rom_cpu_d3 : std_logic_vector( 7 downto 0);
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signal rom_cpu_d4 : std_logic_vector( 7 downto 0);
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signal rom_cpu_d5 : std_logic_vector( 7 downto 0);
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signal rom_cpu_d6 : std_logic_vector( 7 downto 0);
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signal rom_char_a_s : std_logic_vector(11 downto 0);
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signal rom_char_d_s : std_logic_vector(15 downto 0);
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signal rom_sprite_a_s : std_logic_vector(11 downto 0);
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signal rom_sprite_d_s : std_logic_vector(15 downto 0);
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signal
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dac_audio_s,
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dip_block_1_s,
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dip_block_2_s : std_logic_vector( 7 downto 0) := (others => '0');
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signal ps2_scancode : std_logic_vector( 9 downto 0) := (others => '0');
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signal
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vid_rgb,
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vga_rgb : std_logic_vector(15 downto 0) := (others => '0');
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signal but_chute_s : std_logic_vector( 1 downto 0) := (others=>'0');
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begin
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O_PIXCE <= clk_en_5mhz_s;
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but_chute_s <= not but_coin_s(1) & not but_coin_s(0);
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-----------------------------------------------------------------------------
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-- inputs assignments
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-----------------------------------------------------------------------------
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ext_res_s <= I_RESET;
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ext_res_n_s <= not ext_res_s;
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clk_20mhz_s <= CLK_IN;
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-----------------------------------------------------------------------------
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-- Ladybug Machine
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-----------------------------------------------------------------------------
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machine_b : entity work.ladybug_machine
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port map (
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ext_res_n_i => ext_res_n_s,
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clk_20mhz_i => clk_20mhz_s,
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clk_en_5mhz_o => clk_en_5mhz_s,
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tilt_n_i => but_tilt_s(0),
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player_select_n_i => but_select_s,
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player_fire_n_i => but_fire_s,
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player_up_n_i => but_up_s,
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player_right_n_i => but_right_s,
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player_down_n_i => but_down_s,
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player_left_n_i => but_left_s,
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player_bomb_n_i => but_bomb_s,
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right_chute_i => but_chute_s(0),
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left_chute_i => but_chute_s(1),
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dip_block_1_i => dip_block_1_s,
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dip_block_2_i => dip_block_2_s,
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rgb_r_o => O_VIDEO_R,
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rgb_g_o => O_VIDEO_G,
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rgb_b_o => O_VIDEO_B,
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hsync_n_o => O_HSYNC,
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vsync_n_o => O_VSYNC,
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vblank_o => O_VBLANK,
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hblank_o => O_HBLANK,
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audio_o => O_AUDIO,
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rom_cpu_a_o => rom_cpu_a_s,
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rom_cpu_d_i => rom_cpu_d_s,
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rom_char_a_o => rom_char_a_s,
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rom_char_d_i => rom_char_d_s,
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rom_sprite_a_o => rom_sprite_a_s,
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rom_sprite_d_i => rom_sprite_d_s
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);
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-----------------------------------------------------------------------------
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-- Building the DIP Switches - see file ladybug_dip_pack.vhd
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-----------------------------------------------------------------------------
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-- dip_block_1_s <= lb_dip_block_1_c; -- Lady Bug
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-- dip_block_1_s <= do_dip_block_1_c; -- Dorodon
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dip_block_1_s <= ca_dip_block_1_c; -- Cosmic Avenger
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dip_block_2_s <= price_dip_block_2_c; -- Common for all games (coins per game pricing)
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-----------------------------------------------------------------------------
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-- Game ROMs
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-----------------------------------------------------------------------------
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inst_rom_spritel : entity work.rom_sprite_l
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port map (
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CLK => clk_20mhz_s,
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ADDR => rom_sprite_a_s,
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DATA => rom_sprite_d_s( 7 downto 0)
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);
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inst_rom_spriteu : entity work.rom_sprite_u
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port map (
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CLK => clk_20mhz_s,
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ADDR => rom_sprite_a_s,
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DATA => rom_sprite_d_s(15 downto 8)
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);
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inst_rom_charl : entity work.rom_char_l
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port map (
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CLK => clk_20mhz_s,
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ADDR => rom_char_a_s,
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DATA => rom_char_d_s( 7 downto 0)
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);
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inst_rom_charu : entity work.rom_char_u
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port map (
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CLK => clk_20mhz_s,
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ADDR => rom_char_a_s,
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DATA => rom_char_d_s(15 downto 8)
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);
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inst_rom_cpu1 : entity work.rom_cpu1
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port map (
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CLK => clk_20mhz_s,
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ADDR => rom_cpu_a_s(12 downto 0),
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DATA => rom_cpu_d1
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);
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inst_rom_cpu2 : entity work.rom_cpu2
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port map (
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CLK => clk_20mhz_s,
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ADDR => rom_cpu_a_s(12 downto 0),
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DATA => rom_cpu_d2
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);
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inst_rom_cpu3 : entity work.rom_cpu3
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port map (
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CLK => clk_20mhz_s,
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ADDR => rom_cpu_a_s(12 downto 0),
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DATA => rom_cpu_d3
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);
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-----------------------------------------------------------------------------
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-- Program ROMs data mux
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-----------------------------------------------------------------------------
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rom_cpu_d_s <=
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rom_cpu_d1 when rom_cpu_a_s(14 downto 13) = "00" else
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rom_cpu_d2 when rom_cpu_a_s(14 downto 13) = "01" else
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rom_cpu_d3 when rom_cpu_a_s(14 downto 13) = "10" else
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(others=>'0');
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end struct;
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