mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-13 11:24:06 +00:00
20 lines
507 B
VHDL
20 lines
507 B
VHDL
-------------------------------------------------------------------------------
|
|
--
|
|
-- The Data Memory control unit.
|
|
-- All accesses to the Data Memory are managed here.
|
|
--
|
|
-- $Id: dmem_ctrl-c.vhd 295 2009-04-01 19:32:48Z arniml $
|
|
--
|
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
|
--
|
|
-- All rights reserved
|
|
--
|
|
-------------------------------------------------------------------------------
|
|
|
|
configuration t48_dmem_ctrl_rtl_c0 of t48_dmem_ctrl is
|
|
|
|
for rtl
|
|
end for;
|
|
|
|
end t48_dmem_ctrl_rtl_c0;
|