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Gehstock.Mist_FPGA/common/CPU/bc6502/BC6502.qip
2022-09-14 14:46:07 +02:00

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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) bc6502.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) addsub.v ]