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373 lines
9.8 KiB
Verilog
373 lines
9.8 KiB
Verilog
//////////////////////////////////////////////////////////////////////////////////
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//
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// This file is part of the NextZ80 project
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// http://www.opencores.org/cores/nextz80/
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//
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// Filename: NextZ80ALU.v
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// Description: Implementation of Z80 compatible CPU - ALU
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// Version 1.0
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// Creation date: 28Jan2011 - 18Mar2011
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//
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// Author: Nicolae Dumitrache
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// e-mail: ndumitrache@opencores.org
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//
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/////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2011 Nicolae Dumitrache
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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//
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///////////////////////////////////////////////////////////////////////////////////
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//FLAGS: S Z X1 N X2 PV N C
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// OP[4:0]
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// 00000 - ADD D0,D1
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// 00001 - ADC D0,D1
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// 00010 - SUB D0,D1
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// 00011 - SBC D0,D1
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// 00100 - AND D0,D1
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// 00101 - XOR D0,D1
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// 00110 - OR D0,D1
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// 00111 - CP D0,D1
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// 01000 - INC D0
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// 01001 - CPL D0
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// 01010 - DEC D0
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// 01011 - RRD
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// 01100 - RLD
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// 01101 - DAA
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// 01110 - INC16
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// 01111 - DEC16
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// 10000 - ADD16LO
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// 10001 - ADD16HI
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// 10010 -
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// 10011 -
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// 10100 - CCF, pass D0
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// 10101 - SCF, pass D0
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// 10110 -
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// 10111 -
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// 11000 - RLCA D0
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// 11001 - RRCA D0
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// 11010 - RLA D0
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// 11011 - RRA D0
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// 11100 - {ROT, BIT, SET, RES} D0,EXOP
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// RLC D0 C <-- D0 <-- D0[7]
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// RRC D0 D0[0] --> D0 --> C
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// RL D0 C <-- D0 <-- C
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// RR D0 C --> D0 --> C
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// SLA D0 C <-- D0 <-- 0
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// SRA D0 D0[7] --> D0 --> C
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// SLL D0 C <-- D0 <-- 1
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// SRL D0 0 --> D0 --> C
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// 11101 - IN, pass D1
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// 11110 - FLAGS <- D0
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// 11111 - NEG D1
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///////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module ALU8(
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input [7:0] D0,
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input [7:0] D1,
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input [7:0] FIN,
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output reg[7:0] FOUT,
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output reg [15:0] ALU8DOUT,
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input [4:0] OP,
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input [5:0] EXOP, // EXOP[5:4] = 2'b11 for CPI/D/R
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input LDIFLAGS, // zero HF and NF on inc/dec16
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input DSTHI // destination lo
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);
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wire [7:0] daaadjust;
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wire cdaa, hdaa;
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daa daa_adjust(.flags(FIN), .val(D0), .adjust(daaadjust), .cdaa(cdaa), .hdaa(hdaa));
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wire parity = ~^ALU8DOUT[15:8];
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wire zero = ALU8DOUT[15:8] == 0;
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reg csin, cin;
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wire [7:0]d0mux = OP[4:1] == 4'b1111 ? 0 : D0;
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reg [7:0]_d1mux;
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wire [7:0]d1mux = OP[1] ? ~_d1mux : _d1mux;
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wire [8:0]sum;
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wire hf;
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assign {hf, sum[3:0]} = d0mux[3:0] + d1mux[3:0] + cin;
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assign sum[8:4] = d0mux[7:4] + d1mux[7:4] + hf;
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wire overflow = (d0mux[7] & d1mux[7] & !sum[7]) | (!d0mux[7] & !d1mux[7] & sum[7]);
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reg [7:0]dbit;
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always @* begin
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ALU8DOUT = 16'hxxxx;
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FOUT = 8'hxx;
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case({OP[4:2]})
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0,1,4,7: _d1mux = D1;
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2: _d1mux = 1;
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3: _d1mux = daaadjust; // DAA
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6,5: _d1mux = 8'hxx;
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endcase
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case({OP[2:0], FIN[0]})
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0,1,2,7,8,9,10,11,12,13: cin = 0;
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3,4,5,6,14,15: cin = 1;
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endcase
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case(EXOP[3:0])
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0: dbit = 8'b11111110;
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1: dbit = 8'b11111101;
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2: dbit = 8'b11111011;
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3: dbit = 8'b11110111;
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4: dbit = 8'b11101111;
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5: dbit = 8'b11011111;
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6: dbit = 8'b10111111;
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7: dbit = 8'b01111111;
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8: dbit = 8'b00000001;
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9: dbit = 8'b00000010;
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10: dbit = 8'b00000100;
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11: dbit = 8'b00001000;
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12: dbit = 8'b00010000;
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13: dbit = 8'b00100000;
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14: dbit = 8'b01000000;
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15: dbit = 8'b10000000;
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endcase
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case(OP[3] ? EXOP[2:0] : OP[2:0])
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0,5: csin = D0[7];
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1: csin = D0[0];
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2,3: csin = FIN[0];
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4,7: csin = 0;
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6: csin = 1;
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endcase
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case(OP[4:0])
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0,1,2,3,8,10: begin // ADD, ADC, SUB, SBC, INC, DEC
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ALU8DOUT[15:8] = sum[7:0];
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ALU8DOUT[7:0] = sum[7:0];
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FOUT[0] = OP[3] ? FIN[0] : (sum[8] ^ OP[1]); // inc/dec
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FOUT[1] = OP[1];
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FOUT[2] = overflow;
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = hf ^ OP[1];
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = zero & (FIN[6] | ~EXOP[5] | ~DSTHI | OP[3]); //(EXOP[5] & DSTHI) ? (zero & FIN[6]) : zero; // adc16/sbc16
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FOUT[7] = ALU8DOUT[15];
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end
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16,17: begin // ADD16LO, ADD16HI
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ALU8DOUT[15:8] = sum[7:0];
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ALU8DOUT[7:0] = sum[7:0];
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FOUT[0] = sum[8];
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FOUT[1] = OP[1];
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FOUT[2] = FIN[2];
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = hf ^ OP[1];
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = FIN[6];
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FOUT[7] = FIN[7];
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end
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7: begin // CP
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ALU8DOUT[15:8] = sum[7:0];
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FOUT[0] = EXOP[5] ? FIN[0] : !sum[8]; // CPI/D/R
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FOUT[1] = OP[1];
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FOUT[2] = overflow;
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FOUT[3] = D1[3];
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FOUT[4] = !hf;
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FOUT[5] = D1[5];
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FOUT[6] = zero;
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FOUT[7] = ALU8DOUT[15];
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end
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31: begin // NEG
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ALU8DOUT[15:8] = sum[7:0];
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FOUT[0] = !sum[8];
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FOUT[1] = OP[1];
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FOUT[2] = overflow;
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = !hf;
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = zero;
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FOUT[7] = ALU8DOUT[15];
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end
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4: begin // AND
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ALU8DOUT[15:8] = D0 & D1;
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FOUT[0] = 0;
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FOUT[1] = 0;
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FOUT[2] = parity;
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = 1;
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = zero;
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FOUT[7] = ALU8DOUT[15];
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end
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5,6: begin //XOR, OR
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ALU8DOUT[15:8] = OP[0] ? (D0 ^ D1) : (D0 | D1);
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FOUT[0] = 0;
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FOUT[1] = 0;
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FOUT[2] = parity;
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = 0;
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = zero;
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FOUT[7] = ALU8DOUT[15];
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end
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9: begin // CPL
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ALU8DOUT[15:8] = ~D0;
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FOUT[0] = FIN[0];
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FOUT[1] = 1;
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FOUT[2] = FIN[2];
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = 1;
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FOUT[5] = ALU8DOUT[13];
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FOUT[7:6] = FIN[7:6];
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end
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11,12: begin // RLD, RRD
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if(OP[0]) ALU8DOUT = {D0[7:4], D1[3:0], D0[3:0], D1[7:4]};
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else ALU8DOUT = {D0[7:4], D1[7:0], D0[3:0]};
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FOUT[0] = FIN[0];
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FOUT[1] = 0;
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FOUT[2] = parity;
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = 0;
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = zero;
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FOUT[7] = ALU8DOUT[15];
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end
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13: begin // DAA
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ALU8DOUT[15:8] = sum[7:0];
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FOUT[0] = cdaa;
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FOUT[1] = FIN[1];
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FOUT[2] = parity;
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = hdaa;
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = zero;
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FOUT[7] = ALU8DOUT[15];
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end
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14,15: begin // inc/dec 16
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ALU8DOUT = {D0, D1} + (OP[0] ? 16'hffff : 16'h0001);
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FOUT[0] = FIN[0];
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FOUT[1] = LDIFLAGS ? 1'b0 : FIN[1];
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FOUT[2] = ALU8DOUT != 0;
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FOUT[3] = FIN[3];
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FOUT[4] = LDIFLAGS ? 1'b0 : FIN[4];
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FOUT[5] = FIN[5];
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FOUT[6] = FIN[6];
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FOUT[7] = FIN[7];
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end
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20,21: begin // CCF, SCF
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ALU8DOUT[15:8] = D0;
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FOUT[0] = OP[0] ? 1'b1 : !FIN[0];
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FOUT[1] = 1'b0;
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FOUT[2] = FIN[2];
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = OP[0] ? 1'b0 : FIN[0];
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = FIN[6];
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FOUT[7] = FIN[7];
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end
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24,25,26,27, 28: begin // ROT, BIT, RES, SET
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case({OP[2], EXOP[4:3]})
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0,1,2,3,4: // rot - shift
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if(OP[2] ? EXOP[0] : OP[0]){ALU8DOUT[15:8], FOUT[0]} = {csin, D0}; // right
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else {FOUT[0], ALU8DOUT[15:8]} = {D0, csin}; // left
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5,6: begin // BIT, RES
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FOUT[0] = FIN[0];
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ALU8DOUT[15:8] = D0 & dbit;
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end
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7: begin // SET
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FOUT[0] = FIN[0];
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ALU8DOUT[15:8] = D0 | dbit;
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end
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endcase
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ALU8DOUT[7:0] = ALU8DOUT[15:8];
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FOUT[1] = 0;
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FOUT[2] = OP[2] ? (EXOP[3] ? zero : parity) : FIN[2];
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = OP[2] & EXOP[3];
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = OP[2] ? zero : FIN[6];
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FOUT[7] = OP[2] ? ALU8DOUT[15] : FIN[7];
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end
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29: begin // IN, pass D1
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ALU8DOUT = {D1, D1};
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FOUT[0] = FIN[0];
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FOUT[1] = 0;
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FOUT[2] = parity;
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FOUT[3] = ALU8DOUT[11];
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FOUT[4] = 0;
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FOUT[5] = ALU8DOUT[13];
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FOUT[6] = zero;
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FOUT[7] = ALU8DOUT[15];
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end
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30: FOUT = D0; // FLAGS <- D0
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default:;
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endcase
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end
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endmodule
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module daa (
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input [7:0]flags,
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input [7:0]val,
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output wire [7:0]adjust,
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output reg cdaa,
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output reg hdaa
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);
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wire h08 = val[7:4] < 9;
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wire h09 = val[7:4] < 10;
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wire l05 = val[3:0] < 6;
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wire l09 = val[3:0] < 10;
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reg [1:0]aa;
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assign adjust = ({1'b0, aa[1], aa[1], 2'b0, aa[0], aa[0], 1'b0} ^ {8{flags[1]}}) + flags[1];
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always @* begin
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case({flags[0], h08, h09, flags[4], l09})
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5'b00101, 5'b01101: aa = 0;
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5'b00111, 5'b01111, 5'b01000, 5'b01010, 5'b01100, 5'b01110: aa = 1;
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5'b00001, 5'b01001, 5'b10001, 5'b10101, 5'b11001, 5'b11101: aa = 2;
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default: aa = 3;
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endcase
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case({flags[0], h08, h09, l09})
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4'b0011, 4'b0111, 4'b0100, 4'b0110: cdaa = 0;
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default: cdaa = 1;
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endcase
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case({flags[1], flags[4], l05, l09})
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4'b0000, 4'b0010, 4'b0100, 4'b0110, 4'b1110, 4'b1111: hdaa = 1;
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default: hdaa = 0;
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endcase
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end
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endmodule
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module ALU16(
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input [15:0] D0,
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input [7:0] D1,
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output wire[15:0] DOUT,
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input [2:0]OP // 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2
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);
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reg [15:0] mux;
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always @*
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case(OP)
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0: mux = 0; // post inc
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1: mux = 1; // post inc
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2: mux = 2; // post inc
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3: mux = {D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7:0]}; // post inc
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4: mux = 0; // no post inc
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5: mux = 16'hffff; // no post inc
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6: mux = 16'hfffe; // no post inc
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default: mux = 16'hxxxx;
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endcase
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assign DOUT = D0 + mux;
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endmodule
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