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136 lines
3.4 KiB
VHDL
136 lines
3.4 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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library work;
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use work.T80_Pack.all;
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entity Z80 is port
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(
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clk : in std_logic;
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clk_en : in std_logic;
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reset : in std_logic;
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addr : out std_logic_vector(15 downto 0);
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datai : in std_logic_vector(7 downto 0);
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datao : out std_logic_vector(7 downto 0);
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m1 : out std_logic;
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mem_rd : out std_logic;
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mem_wr : out std_logic;
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io_rd : out std_logic;
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io_wr : out std_logic;
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wait_n : in std_logic := '1';
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busrq_n : in std_logic := '1';
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intreq : in std_logic := '0';
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intvec : in std_logic_vector(7 downto 0);
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intack : out std_logic;
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nmi : in std_logic := '0'
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);
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end Z80;
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architecture SYN of Z80 is
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component T80se is
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generic
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(
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Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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T2Write : integer := 1 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
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);
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port
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(
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RESET_n : in std_logic;
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CLK_n : in std_logic;
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CLKEN : in std_logic;
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WAIT_n : in std_logic;
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INT_n : in std_logic;
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NMI_n : in std_logic;
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BUSRQ_n : in std_logic;
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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A : out std_logic_vector(15 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0)
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);
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end component T80se;
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-- Signal Declarations
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signal reset_n : std_logic;
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signal int_n : std_logic;
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signal nmi_n : std_logic;
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signal z80_m1 : std_logic;
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signal z80_memreq : std_logic;
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signal z80_ioreq : std_logic;
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signal z80_rd : std_logic;
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signal z80_wr : std_logic;
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signal z80_datai : std_logic_vector(7 downto 0);
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-- derived signals (outputs we need to read)
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signal z80_memrd : std_logic;
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signal z80_iord : std_logic;
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signal fetch : std_logic;
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begin
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-- simple inversions
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reset_n <= not reset;
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int_n <= not intreq;
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nmi_n <= not nmi;
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-- direct-connect (outputs we need to read)
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m1 <= z80_m1;
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mem_rd <= z80_memrd;
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io_rd <= z80_iord;
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-- memory signals
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z80_memrd <= z80_memreq nor z80_rd;
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mem_wr <= z80_memreq nor z80_wr;
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-- io signals
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z80_iord <= z80_ioreq nor z80_rd;
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io_wr <= z80_ioreq nor z80_wr;
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-- other signals
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fetch <= z80_m1 nor z80_memreq;
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intack <= z80_m1 nor z80_ioreq;
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-- data in mux
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z80_datai <= intvec when ((z80_memrd or z80_iord) = '0') else
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datai;
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Z80_uP : T80se
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generic map
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(
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Mode => 0 -- Z80
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)
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port map
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(
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RESET_n => reset_n,
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CLK_n => clk,
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CLKEN => clk_en,
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WAIT_n => wait_n,
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INT_n => int_n,
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NMI_n => nmi_n,
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BUSRQ_n => busrq_n,
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M1_n => z80_m1,
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MREQ_n => z80_memreq,
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IORQ_n => z80_ioreq,
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RD_n => z80_rd,
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WR_n => z80_wr,
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RFSH_n => open,
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HALT_n => open,
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BUSAK_n => open,
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A => addr,
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DI => z80_datai,
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DO => datao
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);
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end architecture SYN;
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