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82 lines
3.9 KiB
VHDL
82 lines
3.9 KiB
VHDL
-------------------------------------------------------------------------------
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-- CPU86 - VHDL CPU8088 IP core --
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-- Copyright (C) 2002-2008 HT-LAB --
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-- --
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-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
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-- Web : http://www.ht-lab.com --
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-- --
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-- CPU86 is released as open-source under the GNU GPL license. This means --
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-- that designs based on CPU86 must be distributed in full source code --
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-- under the same license. Contact HT-Lab for commercial applications where --
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-- source-code distribution is not desirable. --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file "copying.txt". --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY multiplier IS
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GENERIC(
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WIDTH : integer := 16
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);
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PORT(
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multiplicant : IN std_logic_vector (WIDTH-1 DOWNTO 0);
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multiplier : IN std_logic_vector (WIDTH-1 DOWNTO 0);
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product : OUT std_logic_vector (WIDTH+WIDTH-1 DOWNTO 0); -- result
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twocomp : IN std_logic
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);
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END multiplier ;
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architecture rtl of multiplier is
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function rectify (r : in std_logic_vector (WIDTH-1 downto 0); -- Rectifier for signed multiplication
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twoc : in std_logic) -- Signed/Unsigned
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return std_logic_vector is
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variable rec_v : std_logic_vector (WIDTH-1 downto 0);
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begin
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if ((r(WIDTH-1) and twoc)='1') then
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rec_v := not(r);
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else
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rec_v := r;
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end if;
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return (rec_v + (r(WIDTH-1) and twoc));
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end;
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signal multiplicant_s : std_logic_vector (WIDTH-1 downto 0);
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signal multiplier_s : std_logic_vector (WIDTH-1 downto 0);
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signal product_s : std_logic_vector (WIDTH+WIDTH-1 downto 0); -- Result
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signal sign_s : std_logic;
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begin
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multiplicant_s <= rectify(multiplicant,twocomp);
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multiplier_s <= rectify(multiplier,twocomp);
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sign_s <= multiplicant(WIDTH-1) xor multiplier(WIDTH-1); -- sign product
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product_s <= multiplicant_s * multiplier_s;
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product <= ((not(product_s)) + '1') when (sign_s and twocomp)='1' else product_s;
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end rtl;
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