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110 lines
4.9 KiB
VHDL
110 lines
4.9 KiB
VHDL
-------------------------------------------------------------------------------
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-- CPU86 - VHDL CPU8088 IP core --
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-- Copyright (C) 2002-2008 HT-LAB --
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-- --
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-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
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-- Web : http://www.ht-lab.com --
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-- --
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-- CPU86 is released as open-source under the GNU GPL license. This means --
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-- that designs based on CPU86 must be distributed in full source code --
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-- under the same license. Contact HT-Lab for commercial applications where --
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-- source-code distribution is not desirable. --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file "copying.txt". --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.ALL;
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USE ieee.std_logic_arith.ALL;
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USE work.cpu86pack.ALL;
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ENTITY segregfile IS
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PORT(
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selsreg : IN std_logic_vector (1 DOWNTO 0);
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sibus : IN std_logic_vector (15 DOWNTO 0);
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wrs : IN std_logic;
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reset : IN std_logic;
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clk : IN std_logic;
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sdbus : OUT std_logic_vector (15 DOWNTO 0);
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dimux : IN std_logic_vector (2 DOWNTO 0);
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es_s : OUT std_logic_vector (15 DOWNTO 0);
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cs_s : OUT std_logic_vector (15 DOWNTO 0);
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ss_s : OUT std_logic_vector (15 DOWNTO 0);
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ds_s : OUT std_logic_vector (15 DOWNTO 0)
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);
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END segregfile ;
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architecture rtl of segregfile is
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signal esreg_s : std_logic_vector(15 downto 0);
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signal csreg_s : std_logic_vector(15 downto 0);
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signal ssreg_s : std_logic_vector(15 downto 0);
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signal dsreg_s : std_logic_vector(15 downto 0);
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signal sdbus_s : std_logic_vector (15 downto 0); -- internal sdbus
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signal dimux_s : std_logic_vector (2 downto 0); -- replaced dimux
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begin
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----------------------------------------------------------------------------
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-- 4 registers of 16 bits each
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----------------------------------------------------------------------------
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process (clk,reset)
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begin
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if reset='1' then
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esreg_s <= RESET_ES_C;
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csreg_s <= RESET_CS_C; -- Only CS set after reset
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ssreg_s <= RESET_SS_C;
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dsreg_s <= RESET_DS_C;
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elsif rising_edge(clk) then
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if (wrs='1') then
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case selsreg is
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when "00" => esreg_s <= sibus;
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when "01" => csreg_s <= sibus;
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when "10" => ssreg_s <= sibus;
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when others => dsreg_s <= sibus;
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end case;
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end if;
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end if;
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end process;
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dimux_s <= dimux;
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process (dimux_s,esreg_s,csreg_s,ssreg_s,dsreg_s)
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begin
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case dimux_s is -- Only 2 bits required
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when "100" => sdbus_s <= esreg_s;
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when "101" => sdbus_s <= csreg_s;
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when "110" => sdbus_s <= ssreg_s;
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when others => sdbus_s <= dsreg_s;
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end case;
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end process;
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sdbus <= sdbus_s; -- Connect to entity
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es_s <= esreg_s;
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cs_s <= csreg_s;
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ss_s <= ssreg_s;
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ds_s <= dsreg_s;
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end rtl;
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