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77 lines
2.8 KiB
Systemverilog
77 lines
2.8 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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`default_nettype none
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module MemArbiter(input logic clk,
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input logic reset,
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// Instruction bus
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input logic [19:1] a_m_addr,
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output logic [15:0] a_m_data_in,
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input logic [15:0] a_m_data_out,
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input logic a_m_access,
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output logic a_m_ack,
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input logic a_m_wr_en,
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input logic [1:0] a_m_bytesel,
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// Data bus
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input logic [19:1] b_m_addr,
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output logic [15:0] b_m_data_in,
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input logic [15:0] b_m_data_out,
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input logic b_m_access,
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output logic b_m_ack,
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input logic b_m_wr_en,
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input logic [1:0] b_m_bytesel,
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// Output bus
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output logic [19:1] q_m_addr,
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input logic [15:0] q_m_data_in,
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output logic [15:0] q_m_data_out,
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output logic q_m_access,
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input logic q_m_ack,
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output logic q_m_wr_en,
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output logic [1:0] q_m_bytesel,
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output logic q_b);
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reg grant_to_b;
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reg grant_active;
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assign q_b = (grant_active && grant_to_b) || (!grant_active && b_m_access);
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assign q_m_addr = q_b ? b_m_addr : a_m_addr;
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assign q_m_data_out = q_b ? b_m_data_out : a_m_data_out;
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assign q_m_access = ~q_m_ack & (b_m_access | a_m_access);
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assign q_m_wr_en = q_b ? b_m_wr_en : a_m_wr_en;
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assign q_m_bytesel = q_b ? b_m_bytesel : a_m_bytesel;
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assign a_m_data_in = grant_active & ~grant_to_b ? q_m_data_in : 16'b0;
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assign a_m_ack = grant_active & ~grant_to_b & q_m_ack;
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assign b_m_data_in = grant_active & grant_to_b ? q_m_data_in : 16'b0;
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assign b_m_ack = grant_active & grant_to_b & q_m_ack;
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always_ff @(posedge clk or posedge reset) begin
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if (reset) begin
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grant_active <= 1'b0;
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end else begin
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if (q_m_ack)
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grant_active <= 1'b0;
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else if (!grant_active && (b_m_access || a_m_access)) begin
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grant_active <= 1'b1;
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grant_to_b <= b_m_access;
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end
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end
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end
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endmodule
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