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42 lines
1.2 KiB
Systemverilog
42 lines
1.2 KiB
Systemverilog
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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`default_nettype none
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module SyncPulse(input logic clk,
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input logic reset,
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input logic d,
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output logic p,
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output logic q);
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wire synced;
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reg last_val;
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assign p = synced ^ last_val;
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assign q = last_val;
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always_ff @(posedge clk or posedge reset)
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if (reset)
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last_val <= 1'b0;
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else
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last_val <= synced;
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BitSync BitSync(.clk(clk),
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.reset(reset),
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.d(d),
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.q(synced));
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endmodule
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