mirror of
https://github.com/Gehstock/Mist_FPGA.git
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153 lines
10 KiB
Verilog
153 lines
10 KiB
Verilog
/*******************************************************************************************/
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/** **/
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/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** **/
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/** external interface module Rev 0.0 07/21/2011 **/
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/** **/
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/*******************************************************************************************/
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module extint (data_in, dma_ack, ftch_tran, halt_tran, iack_tran, io_addr_out, io_data_out,
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io_read, io_strobe, io_tran, ivec_rd, mem_addr_out, mem_data_out, mem_rd,
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mem_tran, mem_wr, reti_tran, t1, addr_reg_in, clkc, dmar_reg,
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dout_io_reg, dout_mem_reg, halt_nxt, if_frst, inta_frst, io_data_in,
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ivec_data_in, ld_dmaa, ld_wait, mem_data_in, output_inh, rd_frst, rd_nxt,
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resetb, reti_nxt, tran_sel, wr_frst);
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input clkc; /* main cpu clock */
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input dmar_reg; /* latched dma request */
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input halt_nxt; /* halt cycle identifier */
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input if_frst; /* first part of fetch cycle identifier */
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input inta_frst; /* first part of intack cycle identifier */
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input ld_dmaa; /* load dma request */
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input ld_wait; /* load wait request */
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input output_inh; /* disable cpu outputs */
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input rd_frst; /* first part of read cycle identifier */
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input rd_nxt; /* read cycle identifier */
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input resetb; /* internal reset */
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input reti_nxt; /* reti cycle identifier */
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input wr_frst; /* first part of write cycle identifier */
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input [7:0] dout_io_reg; /* io data output */
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input [7:0] dout_mem_reg; /* mem data output */
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input [7:0] io_data_in; /* i/o input data bus */
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input [7:0] ivec_data_in; /* interrupt vector bus */
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input [7:0] mem_data_in; /* memory input bus */
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input [15:0] addr_reg_in; /* processor logical address bus */
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input [`TTYPE_IDX:0] tran_sel; /* transaction type select */
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output dma_ack; /* dma acknowledge */
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output ftch_tran; /* instruction fetch transaction */
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output halt_tran; /* halt transaction */
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output iack_tran; /* interrupt acknowledge transaction */
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output io_read; /* i/o read enable */
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output io_strobe; /* i/o data strobe */
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output io_tran; /* i/o transaction */
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output ivec_rd; /* interrupt vector enable */
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output mem_rd; /* memory read enable */
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output mem_tran; /* memory transaction */
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output mem_wr; /* memory write enable */
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output reti_tran; /* return from interrupt transaction */
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output t1; /* first clock of transaction */
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output [7:0] data_in; /* data input bus */
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output [7:0] io_data_out; /* i/o output data bus */
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output [7:0] mem_data_out; /* memory output data bus */
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output [15:0] io_addr_out; /* i/o address bus */
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output [15:0] mem_addr_out; /* memory address bus */
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/*****************************************************************************************/
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/* */
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/* signal declarations */
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/* */
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/*****************************************************************************************/
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wire ld_io_addr; /* update io address */
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wire ld_mem_addr; /* update memory address */
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wire [7:0] io_data_out; /* i/o output data bus */
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wire [7:0] mem_data_out; /* memory output data bus */
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reg dma_ack; /* dma acknowledge */
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reg ftch_tran; /* inst fetch transaction */
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reg halt_tran; /* halt transaction */
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reg iack_tran; /* int ack transaction */
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reg io_read; /* i/o read enable */
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reg io_tran; /* i/o transaction */
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reg io_strobe; /* i/o data strobe */
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reg ivec_rd; /* interrupt vector enable */
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reg mem_rd; /* memory read enable */
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reg mem_tran; /* memory transaction */
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reg mem_wr; /* memory write enable */
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reg out_inh_reg; /* latched output inhibit */
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reg reti_tran; /* reti transaction */
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reg t1; /* first clock of transaction */
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reg [7:0] data_in; /* data input bus */
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reg [15:0] io_addr_out; /* i/o address bus */
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reg [15:0] mem_addr_out; /* memory address bus */
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/*****************************************************************************************/
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/* */
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/* misc signals & buses */
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/* */
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/*****************************************************************************************/
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assign io_data_out = (out_inh_reg) ? 8'h00 : dout_io_reg;
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assign mem_data_out = (out_inh_reg) ? 8'h00 : dout_mem_reg;
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assign ld_io_addr = tran_sel[`TT_IO] || output_inh;
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assign ld_mem_addr = tran_sel[`TT_IAK] || tran_sel[`TT_IDL] || tran_sel[`TT_IF] ||
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tran_sel[`TT_MEM] || tran_sel[`TT_STK];
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always @ (iack_tran or io_tran or io_data_in or ivec_data_in or mem_data_in) begin
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case ({iack_tran, io_tran})
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2'b01: data_in = io_data_in;
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2'b10: data_in = ivec_data_in;
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default: data_in = mem_data_in;
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endcase
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end
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/*****************************************************************************************/
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/* */
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/* timing generation */
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/* */
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/*****************************************************************************************/
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always @ (posedge clkc or negedge resetb) begin
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if (!resetb) begin
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dma_ack <= 1'b0;
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ftch_tran <= 1'b0;
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halt_tran <= 1'b0;
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iack_tran <= 1'b0;
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io_addr_out <= 16'h0000;
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io_read <= 1'b0;
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io_tran <= 1'b0;
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mem_addr_out <= 16'h0000;
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mem_tran <= 1'b0;
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out_inh_reg <= 1'b0;
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reti_tran <= 1'b0;
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end
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else if (|tran_sel) begin
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dma_ack <= ld_dmaa && dmar_reg;
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ftch_tran <= tran_sel[`TT_IF];
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halt_tran <= halt_nxt;
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iack_tran <= tran_sel[`TT_IAK];
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if (ld_io_addr) io_addr_out <= (output_inh) ? 16'h0000 : addr_reg_in;
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io_read <= tran_sel[`TT_IO] && rd_nxt;
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io_tran <= tran_sel[`TT_IO];
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if (ld_mem_addr) mem_addr_out <= (output_inh) ? 16'h0000 : addr_reg_in;
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mem_tran <= (tran_sel[`TT_IDL] || tran_sel[`TT_IF] || tran_sel[`TT_MEM] ||
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tran_sel[`TT_STK]) && !output_inh;
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out_inh_reg <= output_inh;
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reti_tran <= reti_nxt;
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end
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end
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always @ (posedge clkc or negedge resetb) begin
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if (!resetb) begin
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io_strobe <= 1'b0;
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ivec_rd <= 1'b0;
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mem_rd <= 1'b0;
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mem_wr <= 1'b0;
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t1 <= 1'b0;
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end
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else begin
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io_strobe <= io_tran && (rd_frst || wr_frst);
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ivec_rd <= iack_tran && inta_frst;
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mem_rd <= (if_frst || (mem_tran && rd_frst)) && ld_wait;
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mem_wr <= mem_tran && wr_frst;
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t1 <= |tran_sel && !(halt_nxt || dmar_reg);
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end
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end
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endmodule |