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20 lines
270 B
VHDL
20 lines
270 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity ls17 is
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port
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(
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a1, a2, a3, a4, a5, a6 : in std_logic;
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y1, y2, y3, y4, y5, y6 : out std_logic
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);
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end ls17;
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architecture arch of ls17 is
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begin
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y1 <= a1;
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y2 <= a2;
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y3 <= a3;
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y4 <= a4;
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y5 <= a5;
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y6 <= a6;
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end arch; |