mirror of
https://github.com/Gehstock/Mist_FPGA.git
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145 lines
4.2 KiB
Systemverilog
145 lines
4.2 KiB
Systemverilog
//============================================================================
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//
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// SystemVerilog implementation of the Konami 082 custom chip, used by
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// several Konami arcade PCBs to generate video timings
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// Copyright (C) 2020 Ace
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS IN THE SOFTWARE.
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//
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//============================================================================
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//Chip pinout:
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/* _____________
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_| |_
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VCC |_|1 28|_| VCC
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_| |_
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h1 |_|2 27|_| GND
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_| |_
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h2 |_|3 26|_| v1
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_| |_
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h4 |_|4 25|_| v2
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_| |_
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h8 |_|5 24|_| v4
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_| |_
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h16 |_|6 23|_| v8
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_| |_
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h32 |_|7 22|_| v16
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_| |_
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h64 |_|8 21|_| v32
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_| |_
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h128 |_|9 20|_| v64
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_| |_
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n_h256 |_|10 19|_| v128
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_| |_
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h256 |_|11 18|_| n_vsync
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_| |_
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VCC |_|12 17|_| sync
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_| |_
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clk |_|13 16|_| vblk
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_| |_
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GND |_|14 15|_| n_vblk
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|_____________|
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Note: Pins 1, 12 and 27 may control other features of the 082 - these, if any, have not
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been modelled yet.
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*/
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module k082
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(
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input clk,
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input clk_en,
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output n_vsync, sync,
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output n_hsync, //Not exposed on the original chip
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output reg vblk = 1,
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output n_vblk,
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output h1, h2, h4, h8, h16, h32, h64, h128, h256, n_h256,
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output v1, v2, v4, v8, v16, v32, v64, v128,
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output h1_en, h2_en, h4_en, h8_en, h16_en, h32_en, h64_en, h128_en, h256_en, n_h256_en
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);
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reg [8:0] h_cnt = 9'd0;
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reg [8:0] v_cnt = 9'd0;
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always_ff @(posedge clk) if (clk_en) begin
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h_cnt <= h_cnt + 9'd1;
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case(h_cnt)
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48: begin
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v_cnt <= v_cnt + 9'd1;
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end
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176: begin
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case(v_cnt)
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16: begin
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vblk <= 0;
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v_cnt <= v_cnt + 9'd1;
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end
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271: begin
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vblk <= 0;
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v_cnt <= v_cnt + 9'd1;
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end
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495: begin
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vblk <= 1;
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v_cnt <= v_cnt + 9'd1;
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end
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511: v_cnt <= 9'd248;
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default: v_cnt <= v_cnt + 9'd1;
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endcase
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end
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511: h_cnt <= 9'd128;
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default: ;
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endcase
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end
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assign n_vblk = ~vblk;
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assign n_hsync = ~(h_cnt > 175 && h_cnt < 208);
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assign n_vsync = v_cnt[8];
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assign sync = n_hsync ^ n_vsync;
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assign h1 = h_cnt[0];
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assign h2 = h_cnt[1];
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assign h4 = h_cnt[2];
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assign h8 = h_cnt[3];
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assign h16 = h_cnt[4];
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assign h32 = h_cnt[5];
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assign h64 = h_cnt[6];
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assign h128 = h_cnt[7];
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assign h256 = ~h_cnt[8];
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assign n_h256 = h_cnt[8];
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assign h1_en = !h_cnt[0];
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assign h2_en = h_cnt[1:0] == 2'b01;
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assign h4_en = h_cnt[2:0] == 3'b011;
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assign h8_en = h_cnt[3:0] == 4'b0111;
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assign h16_en = h_cnt[4:0] == 5'b01111;
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assign h32_en = h_cnt[5:0] == 6'b011111;
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assign h64_en = h_cnt[6:0] == 7'b0111111;
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assign h128_en = h_cnt[7:0] == 8'b01111111;
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assign h256_en = h_cnt[8:0] == 9'b111111111;
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assign n_h256_en = h_cnt[8:0] == 9'b011111111;
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assign v1 = v_cnt[0];
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assign v2 = v_cnt[1];
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assign v4 = v_cnt[2];
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assign v8 = v_cnt[3];
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assign v16 = v_cnt[4];
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assign v32 = v_cnt[5];
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assign v64 = v_cnt[6];
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assign v128 = v_cnt[7];
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endmodule
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