mirror of
https://github.com/Gehstock/Mist_FPGA.git
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590 lines
18 KiB
VHDL
590 lines
18 KiB
VHDL
-- Copyright (c) 2015, $ME
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-- All rights reserved.
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--
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-- Redistribution and use in source and synthezised forms, with or without modification, are permitted
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-- provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice, this list of conditions
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-- and the following disclaimer.
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--
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-- 2. Redistributions in synthezised form must reproduce the above copyright notice, this list of conditions
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-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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-- WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- KC87 Toplevel
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity kc87 is
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port(
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vgaclock : in std_logic;--40
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clk : in std_logic;--50
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ResetKey : in std_logic;
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VGA_R : out std_logic_vector(3 downto 0);
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VGA_G : out std_logic_vector(3 downto 0);
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VGA_B : out std_logic_vector(3 downto 0);
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VGA_HS : out std_logic;
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VGA_VS : out std_logic;
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PS2_CLK : inout std_logic;
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PS2_DAT : inout std_logic;
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UART_TXD : out std_logic;
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UART_RXD : in std_logic;
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-- Reset_n : in std_logic;
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-- clk : in std_logic;
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-- nmi_n : in std_logic;
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SD_DAT : in std_logic;
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SD_DAT3 : out std_logic;
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SD_CMD : out std_logic;
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SD_CLK : out std_logic
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);
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end kc87;
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architecture struct of kc87 is
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signal int_n : std_logic;
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signal busrq_n : std_logic;
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signal m1_n : std_logic;
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signal mreq_n : std_logic;
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signal iorq_n : std_logic;
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signal rd_n : std_logic;
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signal wr_n : std_logic;
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signal halt_n : std_logic;
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signal wait_n : std_logic;
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signal busak_n : std_logic;
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signal cpu_addr : std_logic_vector(15 downto 0);
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signal cpu_do : std_logic_vector(7 downto 0);
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signal cpu_di : std_logic_vector(7 downto 0);
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signal bootRom_d : std_logic_vector(7 downto 0);
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signal monitorRom_d : std_logic_vector(7 downto 0);
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signal osRom_d : std_logic_vector(7 downto 0);
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signal ram_di : std_logic_vector(7 downto 0);
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signal ram_do : std_logic_vector(7 downto 0);
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signal vram_d : std_logic_vector(7 downto 0);
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signal cram_d : std_logic_vector(7 downto 0);
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signal uart_d : std_logic_vector(7 downto 0);
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signal sdcard_d : std_logic_vector(7 downto 0);
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signal ctc_d : std_logic_vector(7 downto 0);
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signal pio1_d : std_logic_vector(7 downto 0);
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signal pio2_d : std_logic_vector(7 downto 0);
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signal sysctl_d : std_logic_vector(7 downto 0);
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-- signal mirrorOS : std_logic;
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signal ram_cs_n : std_logic;
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signal vram_cs_n : std_logic;
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signal cram_cs_n : std_logic;
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signal ctc_cs_n : std_logic;
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signal uart_cs_n : std_logic;
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-- signal monRom_cs_n : std_logic;
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-- signal osRom_cs_n : std_logic;
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signal bootRom_cs_n : std_logic;
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signal sysctl_cs_n : std_logic;
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signal sdcard_cs_n : std_logic;
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-- signal vgaclock : std_logic;
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signal vgaramaddr : std_logic_vector(9 downto 0);
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signal vgacoldata : std_logic_vector(7 downto 0);
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signal vgachardata : std_logic_vector(7 downto 0);
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signal reset_n : std_logic;
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signal resetInt : std_logic;
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-- signal clk : std_logic;
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signal nmi_n : std_logic;
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signal pio1_cs_n : std_logic;
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signal pio2_cs_n : std_logic;
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signal pio1_aIn : std_logic_vector(7 downto 0);
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signal pio1_aOut : std_logic_vector(7 downto 0);
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signal pio1_aRdy : std_logic;
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signal pio1_aStb : std_logic;
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signal pio1_bIn : std_logic_vector(7 downto 0);
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signal pio1_bOut : std_logic_vector(7 downto 0);
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signal pio1_bRdy : std_logic;
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signal pio1_bStb : std_logic;
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signal pio2_aIn : std_logic_vector(7 downto 0);
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signal pio2_aOut : std_logic_vector(7 downto 0);
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signal pio2_aRdy : std_logic;
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signal pio2_aStb : std_logic;
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signal pio2_bIn : std_logic_vector(7 downto 0);
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signal pio2_bOut : std_logic_vector(7 downto 0);
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signal pio2_bRdy : std_logic;
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signal pio2_bStb : std_logic;
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signal iei : std_logic_vector(2 downto 0);
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signal ieo : std_logic_vector(2 downto 0);
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signal int : std_logic_vector(2 downto 0) := (others => '1');
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signal intAckCTC : std_logic;
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signal intAckPio1 : std_logic;
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signal intAckPio2 : std_logic;
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signal ctcTcTo : std_logic_vector(3 downto 0);
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signal ctcClkTrg : std_logic_vector(3 downto 0);
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signal ledbuff : std_logic_vector(7 downto 0);
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signal leddelay : integer range 0 to 400000;
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signal kmatrixXout : std_logic_vector(7 downto 0);
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signal kmatrixXin : std_logic_vector(7 downto 0);
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signal kmatrixYout : std_logic_vector(7 downto 0);
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signal kmatrixYin : std_logic_vector(7 downto 0);
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signal clkDiv : integer range 0 to 50000000 := 0;
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signal clkEn : std_logic := '0';
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signal clkSlowdown : std_logic := '0';
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signal ioSel : boolean;
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signal memSel : boolean;
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signal kcSysClk : std_logic;
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signal ledDisplay : std_logic_vector(15 downto 0);
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signal intAddr : std_logic_vector(15 downto 0);
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signal testAddr1 : std_logic_vector(15 downto 0);
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signal testAddr2 : std_logic_vector(15 downto 0);
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signal testAddr3 : std_logic_vector(15 downto 0);
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signal intAckPeriph : std_logic_vector(7 downto 0);
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signal intPeriph : std_logic_vector(7 downto 0);
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signal RETI_n : std_logic;
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signal IntE : std_logic;
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signal lastIntE : std_logic;
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-- signal lastM1Addr : std_logic_vector(15 downto 0);
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signal int_SD_DAT3 : std_logic;
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signal int_SD_CLK : std_logic;
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signal int_SD_CMD : std_logic;
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begin
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SD_DAT3 <= int_SD_DAT3;
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SD_CLK <= int_SD_CLK;
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SD_CMD <= int_SD_CMD;
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wait_n <= '1';
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busrq_n <= '1';
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nmi_n <= '1';
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-- interrupt-vektoren und letzten angesprungenen interrupt merken
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process
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begin
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wait until rising_edge(clk);
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if m1_n='0' and rd_n = '0' and ram_cs_n = '0' then
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lastIntE <= intE;
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-- lastM1Addr <= cpu_addr;
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if (lastIntE='1' and intE='0') then
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intAddr <= cpu_addr;
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end if;
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end if;
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ledbuff <= intPeriph or ledbuff;
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if (leddelay=400000) then
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ledbuff <= "00000000";
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leddelay <= 0;
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else
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leddelay <= leddelay + 1;
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end if;
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end process;
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-- reset-logik
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process (reset_n, clk, ResetKey)
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begin
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if reset_n = '0' or ResetKey='0' then
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resetInt <= '0';
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-- mirrorOS <= '1';
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elsif rising_edge(clk) then
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resetInt <= '1';
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if cpu_addr(15) = '1' then
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-- mirrorOS <= '0';
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end if;
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end if;
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end process;
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memSel <= mreq_n = '0';
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-- diverse cs signale
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-- monRom_cs_n <= '0' when (cpu_addr(15 downto 10) = "100000") and memSel else '1';
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-- ram_cs_n <= cpu_addr(15) or mreq_n;
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ram_cs_n <= mreq_n;
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cram_cs_n <= '0' when (cpu_addr(15 downto 10) = "111010") and memSel else '1';
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vram_cs_n <= '0' when (cpu_addr(15 downto 10) = "111011") and memSel else '1';
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-- osRom_cs_n <= '0' when (cpu_addr(15 downto 12) = "1111" and memSel) else '1';
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bootRom_cs_n <= '0' when (sysctl_d(0)='0' and cpu_addr(15 downto 14)="00" and memSel) else '1';
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ioSel <= iorq_n = '0' and m1_n='1';
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intAckCTC <= '0' when intAckPeriph(3 downto 0)="0000" else '1';
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intAckPio1 <= '0' when intAckPeriph(5 downto 4)="00" else '1';
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intAckPio2 <= '0' when intAckPeriph(7 downto 6)="00" else '1';
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uart_cs_n <= '0' when cpu_addr(7 downto 1) = "0000000" and ioSel else '1';
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sysctl_cs_n <= '0' when cpu_addr(7 downto 0) = "00000010" and ioSel else '1';
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ctc_cs_n <= '0' when cpu_addr(7 downto 3) = "10000" and ioSel else '1';
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pio1_cs_n <= '0' when cpu_addr(7 downto 3) = "10001" and ioSel else '1';
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pio2_cs_n <= '0' when cpu_addr(7 downto 3) = "10010" and ioSel else '1';
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sdcard_cs_n <= '0' when cpu_addr(7 downto 2) = "000001" and ioSel else '1';
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-- cpu data-in multiplexer
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cpu_di <=
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-- "00000000" when mirrorOS='1' else
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-- osRom_d when osRom_cs_n='0' else
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-- monitorRom_d when monRom_cs_n = '0' else
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ctc_d when (ctc_cs_n = '0' or intAckCTC='1') else
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pio1_d when (pio1_cs_n = '0' or intAckPio1='1') else
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pio2_d when (pio2_cs_n = '0' or intAckPio2='1') else
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uart_d when uart_cs_n='0' else
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sdcard_d when sdcard_cs_n='0' else
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bootRom_d when bootRom_cs_n='0' else
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sysctl_d when (sysctl_cs_n = '0') else
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cram_d when cram_cs_n = '0' else
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vram_d when vram_cs_n = '0' else
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-- osRom_d;
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ram_do;
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-- process
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-- begin
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-- wait until rising_edge(clk);
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--
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-- clkSlowdown <= SW(0);
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-- clkEn <= '0';
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-- if (clkDiv=1 or clkSlowdown='1') then
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-- clkDiv <= 0;
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-- clkEn <= KEY(1);
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-- else
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-- clkDiv <= clkDiv + 1;
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-- end if;
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-- end process;
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-- teh cpu
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cpu : entity work.T80se
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generic map(Mode => 0, T2Write => 1, IOWait => 0)
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port map(
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RESET_n => resetInt,
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CLK_n => clk,
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CLKEN => kcSysClk or sysctl_d(1),
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WAIT_n => wait_n,
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INT_n => int_n,
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NMI_n => nmi_n,
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BUSRQ_n => busrq_n,
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M1_n => m1_n,
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MREQ_n => mreq_n,
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IORQ_n => iorq_n,
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RD_n => rd_n,
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WR_n => wr_n,
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RFSH_n => open,
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HALT_n => halt_n,
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BUSAK_n => busak_n,
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A => cpu_addr,
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DI => cpu_di,
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DO => cpu_do,
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RETI_n => RETI_n,
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IntE => IntE
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);
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--!!! Check active Lows
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-- interupt controller
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intController : entity work.intController
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port map (
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clk => clk,
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res => resetInt,--N
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int => int_n,--N
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intPeriph => intPeriph,
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intAck => intAckPeriph,
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cpuDIn => cpu_di,
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m1 => m1_n,--N
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iorq => iorq_n,--N
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rd => rd_n,--N
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RETI_n => RETI_n
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);
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-- ctc
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ctc : entity work.ctc
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-- generic map(
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-- sysclk => 125000
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-- )
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port map (
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clk => clk,
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res_n => resetInt,
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en => ctc_cs_n,
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dIn => cpu_do,
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dOut => ctc_d,
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cs => cpu_addr(1 downto 0),
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m1_n => m1_n,
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iorq_n => iorq_n,
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rd_n => rd_n,
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int => intPeriph(3 downto 0),
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intAck => intAckPeriph(3 downto 0),
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clk_trg => ctcClkTrg,
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zc_to => ctcTcTo,
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kcSysClk => kcSysClk
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);
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-- ctc-aus und eingänge verdrahten
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ctcClkTrg(2 downto 0) <= (others => '0');
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ctcClkTrg(3) <= ctcTcTo(2);
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-- System PIO
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pio1 : entity work.pio
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port map (
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clk => clk,
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res_n => resetInt,
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en => '1',
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dIn => cpu_do,
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dOut => pio1_d,
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baSel => cpu_addr(0),
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cdSel => cpu_addr(1),
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cs_n => pio1_cs_n,
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m1_n => m1_n,
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iorq_n => iorq_n,
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rd_n => rd_n,
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intAck => intAckPeriph(5 downto 4),
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int => intPeriph(5 downto 4),
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aIn => pio1_aIn,
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aOut => pio1_aOut,
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aRdy => pio1_aRdy,
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aStb => pio1_aStb,
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bIn => pio1_bIn,
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bOut => pio1_bOut,
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bRdy => pio1_bRdy,
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bStb => '1'
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);
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pio1_aStb <= '1';
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pio1_aIn <= (others => '1');
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pio1_bIn <= (others => '1');
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-- Keyboard PIO
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pio2 : entity work.pio
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port map (
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clk => clk,
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res_n => resetInt,
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en => '1',
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dIn => cpu_do,
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dOut => pio2_d,
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baSel => cpu_addr(0),
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cdSel => cpu_addr(1),
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cs_n => pio2_cs_n,
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m1_n => m1_n,
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iorq_n => iorq_n,
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rd_n => rd_n,
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intAck => intAckPeriph(7 downto 6),
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int => intPeriph(7 downto 6),
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aIn => kmatrixXout,
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aOut => kmatrixXin,
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aRdy => pio2_aRdy,
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aStb => '1',
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bIn => kmatrixYout,
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bOut => kmatrixYin,
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bRdy => pio2_bRdy,
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bStb => '1'
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);
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-- Syscontrol port:
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-- 0: 0 Bootrom einblenden
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-- 0: 1 Bootrom aus
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-- 1: 0 Turbo aus
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-- 1: 1 Turbo an
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-- 2: 0 Schreibschutz Ram ab 8000 aus
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-- 2: 1 Schreibschutz Ram ab 8000 an
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syscontrol : entity work.pport
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port map (
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clk => clk,
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ce_n => sysctl_cs_n,
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wr_n => wr_n,
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res_n => resetInt,
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dIn => cpu_do,
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pOut => sysctl_d
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);
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ram : entity work.mram
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port map (
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clock => clk,
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address => cpu_addr(14 downto 0),
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data => cpu_do,
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wren => not (wr_n or ram_cs_n or (sysctl_d(2) and cpu_addr(15)) or (sysctl_d(2) and cpu_addr(15))),
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rden => not(rd_n and ram_cs_n),
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q => ram_do
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);
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-- sram signale
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-- ram_d <= SRAM_DQ(7 downto 0);
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-- SRAM_ADDR(15 downto 0) <= cpu_addr(15 downto 0);
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-- SRAM_CE_N <= '0';
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-- SRAM_OE_N <= rd_n or ram_cs_n;
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-- SRAM_WE_N <= wr_n or ram_cs_n or (sysctl_d(2) and cpu_addr(15)) or (sysctl_d(2) and cpu_addr(15)); -- wp fuer oberen ram wenn sysctl_d(2)
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-- process -- DQ einen halben takt verzögern (ansonsten SRAM-Timingproblem wegen zu kurzem WR)
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-- begin
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-- wait until falling_edge(clk);
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-- if (wr_n='0' and ram_cs_n='0') then
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-- SRAM_DQ(7 downto 0) <= cpu_do;
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-- else
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-- SRAM_DQ <= (others => 'Z');
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-- end if;
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-- end process;
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-- video blockram
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vram : entity work.dualsram
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generic map (
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AddrWidth => 10
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)
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port map (
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clk1 => clk,
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addr1 => cpu_addr(9 downto 0),
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din1 => cpu_do,
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dout1 => vram_d,
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ce1_n => vram_cs_n,
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we1_n => wr_n,
|
|
|
|
clk2 => vgaclock,
|
|
addr2 => vgaramaddr,
|
|
din2 => "00000000",
|
|
dout2 => vgachardata,
|
|
ce2_n => '0',
|
|
we2_n => '1'
|
|
);
|
|
|
|
-- color-video blockram
|
|
cram : entity work.dualsram
|
|
generic map (
|
|
AddrWidth => 10
|
|
)
|
|
port map (
|
|
clk1 => clk,
|
|
addr1 => cpu_addr(9 downto 0),
|
|
din1 => cpu_do,
|
|
dout1 => cram_d,
|
|
ce1_n => cram_cs_n,
|
|
we1_n => wr_n,
|
|
|
|
clk2 => vgaclock,
|
|
addr2 => vgaramaddr,
|
|
din2 => "00000000",
|
|
dout2 => vgacoldata,
|
|
ce2_n => '0',
|
|
we2_n => '1'
|
|
);
|
|
|
|
-- bootrom : entity work.bootrom
|
|
-- port map (
|
|
-- clk => clk,
|
|
-- addr => cpu_addr(13 downto 0),
|
|
-- data => bootRom_d
|
|
-- );
|
|
|
|
-- startrom
|
|
monitor : entity work.monitor
|
|
port map (
|
|
clk => clk,
|
|
addr => cpu_addr(13 downto 0),
|
|
data => bootRom_d
|
|
);
|
|
|
|
-- vga-comtroller
|
|
video : entity work.video
|
|
port map (
|
|
clk => vgaclock,
|
|
red => VGA_R,
|
|
green => VGA_G,
|
|
blue => VGA_B,
|
|
hsync => VGA_HS,
|
|
vsync => VGA_VS,
|
|
|
|
ramAddr => vgaramaddr,
|
|
colData => vgacoldata,
|
|
charData => vgachardata,
|
|
scanLine => '1'
|
|
);
|
|
|
|
-- ps/2 interface
|
|
ps2kc : entity work.ps2kc
|
|
port map (
|
|
clk => clk,
|
|
res => '1',--resetInt,
|
|
ps2clk => PS2_CLK,
|
|
ps2data => PS2_DAT,
|
|
data => open,
|
|
ps2code => open,
|
|
ps2rcvd => open,
|
|
matrixXout => kmatrixXout,
|
|
matrixXin => kmatrixXin,
|
|
matrixYout => kmatrixYout,
|
|
matrixYin => kmatrixYin
|
|
);
|
|
|
|
-- uart
|
|
uart : entity work.uart
|
|
-- generic map (
|
|
-- sysclk => 12500000
|
|
-- )
|
|
port map (
|
|
clk => clk,
|
|
|
|
cs_n => uart_cs_n,
|
|
rd_n => rd_n,
|
|
wr_n => wr_n,
|
|
|
|
addr => cpu_addr(0 downto 0),
|
|
|
|
dIn => cpu_do,
|
|
dOut => UART_D,
|
|
|
|
txd => UART_TXD,
|
|
rxd => UART_RXD
|
|
);
|
|
|
|
-- sdcard interface
|
|
-- sdcard : entity work.spi
|
|
-- port map (
|
|
-- clk => clk,
|
|
|
|
-- cs_n => sdcard_cs_n,
|
|
-- wr_n => wr_n,
|
|
-- addr => cpu_addr(1 downto 0),
|
|
|
|
-- dIn => cpu_do,
|
|
-- dOut => sdcard_d,
|
|
|
|
-- spi_cs => int_SD_DAT3,
|
|
-- spi_clk => int_SD_CLK,
|
|
-- spi_miso => SD_DAT,
|
|
-- spi_mosi => int_SD_CMD
|
|
-- );
|
|
|
|
end; |