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90 lines
1.9 KiB
Systemverilog
90 lines
1.9 KiB
Systemverilog
// Get current OP from row & col
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module aluGetOp( input [15:0] row, input [2:0] col, input isCorf,
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output logic [4:0] aluOp);
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always_comb begin
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aluOp = 'X;
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unique case( col)
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1: aluOp = OP_AND;
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5: aluOp = OP_EXT;
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default:
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unique case( 1'b1)
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row[1]:
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unique case( col)
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2: aluOp = OP_SUB;
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3: aluOp = OP_SUBC;
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4,6: aluOp = OP_SLAA;
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endcase
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row[2]:
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unique case( col)
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2: aluOp = OP_ADD;
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3: aluOp = OP_ADDC;
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4: aluOp = OP_ASR;
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endcase
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row[3]:
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unique case( col)
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2: aluOp = OP_ADDX;
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3: aluOp = isCorf ? OP_ABCD : OP_ADD;
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4: aluOp = OP_ASL;
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endcase
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row[4]:
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aluOp = ( col == 4) ? OP_LSL : OP_AND;
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row[5],
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row[6]:
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unique case( col)
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2: aluOp = OP_SUB;
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3: aluOp = OP_SUBC;
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4: aluOp = OP_LSR;
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endcase
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row[7]: // MUL
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unique case( col)
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2: aluOp = OP_SUB;
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3: aluOp = OP_ADD;
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4: aluOp = OP_ROXR;
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endcase
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row[8]:
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// OP_AND For EXT.L
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// But would be more efficient to change ucode and use column 1 instead of col3 at ublock extr1!
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unique case( col)
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2: aluOp = OP_EXT;
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3: aluOp = OP_AND;
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4: aluOp = OP_ROXR;
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endcase
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row[9]:
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unique case( col)
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2: aluOp = OP_SUBX;
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3: aluOp = OP_SBCD;
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4: aluOp = OP_ROL;
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endcase
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row[10]:
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unique case( col)
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2: aluOp = OP_SUBX;
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3: aluOp = OP_SUBC;
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4: aluOp = OP_ROR;
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endcase
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row[11]:
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unique case( col)
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2: aluOp = OP_SUB0;
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3: aluOp = OP_SUB0;
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4: aluOp = OP_ROXL;
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endcase
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row[12]: aluOp = OP_ADDX;
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row[13]: aluOp = OP_EOR;
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row[14]: aluOp = (col == 4) ? OP_EOR : OP_OR;
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row[15]: aluOp = (col == 3) ? OP_ADD : OP_OR; // OP_ADD used by DBcc
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endcase
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endcase
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end
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endmodule
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