mirror of
https://github.com/Gehstock/Mist_FPGA.git
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133 lines
4.8 KiB
VHDL
133 lines
4.8 KiB
VHDL
-------------------------------------------------------------------------------
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-- CPU86 - VHDL CPU8088 IP core --
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-- Copyright (C) 2002-2008 HT-LAB --
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-- --
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-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
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-- Web : http://www.ht-lab.com --
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-- --
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-- CPU86 is released as open-source under the GNU GPL license. This means --
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-- that designs based on CPU86 must be distributed in full source code --
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-- under the same license. Contact HT-Lab for commercial applications where --
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-- source-code distribution is not desirable. --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file "copying.txt". --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY formatter IS
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PORT(
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lutbus : IN std_logic_vector (15 DOWNTO 0);
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mux_addr : OUT std_logic_vector (2 DOWNTO 0);
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mux_data : OUT std_logic_vector (3 DOWNTO 0);
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mux_reg : OUT std_logic_vector (2 DOWNTO 0);
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nbreq : OUT std_logic_vector (2 DOWNTO 0)
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);
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END formatter ;
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ARCHITECTURE struct OF formatter IS
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-- Architecture declarations
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SIGNAL dout : std_logic_vector(15 DOWNTO 0);
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SIGNAL dout4 : std_logic_vector(7 DOWNTO 0);
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SIGNAL dout5 : std_logic_vector(7 DOWNTO 0);
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SIGNAL muxout : std_logic_vector(7 DOWNTO 0);
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SIGNAL mw_I1temp_din : std_logic_vector(15 DOWNTO 0);
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-- Component Declarations
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COMPONENT a_table
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PORT (
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addr : IN std_logic_vector (15 DOWNTO 0);
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dout : OUT std_logic_vector (2 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT d_table
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PORT (
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addr : IN std_logic_vector (15 DOWNTO 0);
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dout : OUT std_logic_vector (3 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT m_table
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PORT (
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ireg : IN std_logic_vector (7 DOWNTO 0);
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modrrm : IN std_logic_vector (7 DOWNTO 0);
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muxout : OUT std_logic_vector (7 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT n_table
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PORT (
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addr : IN std_logic_vector (15 DOWNTO 0);
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dout : OUT std_logic_vector (2 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT r_table
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PORT (
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addr : IN std_logic_vector (15 DOWNTO 0);
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dout : OUT std_logic_vector (2 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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dout <= dout4 & muxout;
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mw_I1temp_din <= lutbus;
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i1combo_proc: PROCESS (mw_I1temp_din)
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VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);
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BEGIN
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temp_din := mw_I1temp_din(15 DOWNTO 0);
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dout5 <= temp_din(7 DOWNTO 0);
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dout4 <= temp_din(15 DOWNTO 8);
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END PROCESS i1combo_proc;
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-- Instance port mappings.
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I2 : a_table
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PORT MAP (
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addr => dout,
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dout => mux_addr
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);
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I3 : d_table
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PORT MAP (
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addr => dout,
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dout => mux_data
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);
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I6 : m_table
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PORT MAP (
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ireg => dout4,
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modrrm => dout5,
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muxout => muxout
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);
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I4 : n_table
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PORT MAP (
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addr => dout,
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dout => nbreq
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);
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I5 : r_table
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PORT MAP (
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addr => dout,
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dout => mux_reg
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);
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END struct;
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