mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-19 09:18:02 +00:00
152 lines
5.0 KiB
Plaintext
152 lines
5.0 KiB
Plaintext
// Copyright Jamie Iles, 2017
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//
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// This file is part of s80x86.
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//
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// s80x86 is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// s80x86 is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with s80x86. If not, see <http://www.gnu.org/licenses/>.
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// MOV 0x88 r/m := r (8-bit)
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.at 0x88;
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mar_write, mar_wr_sel EA, width W8, jmp_rm_reg_mem mov88_reg;
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// MOV 0x89 r/m := r (16-bit)
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.at 0x89;
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mar_write, mar_wr_sel EA, jmp_rm_reg_mem mov88_reg;
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.auto_address;
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mov88_reg:
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b_sel RB, alu_op SELB, rd_sel_source MODRM_RM_REG,
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width WAUTO, next_instruction;
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mov88_mem:
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b_sel RB, alu_op SELB, mdr_write, segment DS, jmp write_complete;
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// MOV 0x8a r := r/m (8-bit)
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.at 0x8a;
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mar_write, mar_wr_sel EA, ra_modrm_rm_reg, width W8,
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jmp_rm_reg_mem mov8a_reg, segment DS, a_sel RA;
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// MOV 0x8b r := r/m (16-bit)
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.at 0x8b;
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mar_write, mar_wr_sel EA, ra_modrm_rm_reg,
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jmp_rm_reg_mem mov8a_reg, a_sel RA, segment DS;
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.auto_address;
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mov8a_reg:
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a_sel RA, ra_modrm_rm_reg, alu_op SELA,
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rd_sel_source MODRM_REG, width WAUTO,
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next_instruction;
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mov8a_mem:
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mem_read, width WAUTO, segment DS;
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rd_sel_source MODRM_REG, a_sel MDR, alu_op SELA, width WAUTO,
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next_instruction;
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// MOV 0xc6 r/m := immed8
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.at 0xc6;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg c6_dispatch;
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// MOV 0xc7 r/m := immed16
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.at 0xc7;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg c6_dispatch;
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.auto_address;
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c6_dispatch:
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jmp_rm_reg_mem movc6_reg; // reg == 0
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next_instruction; // reg == 1
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next_instruction; // reg == 2
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next_instruction; // reg == 3
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next_instruction; // reg == 4
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next_instruction; // reg == 5
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next_instruction; // reg == 6
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next_instruction; // reg == 7
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movc6_reg:
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b_sel IMMEDIATE, alu_op SELB,
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rd_sel_source MODRM_RM_REG, width WAUTO,
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next_instruction;
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movc6_mem:
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b_sel IMMEDIATE, alu_op SELB, mdr_write, segment DS, jmp write_complete;
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#define MOV_REG_IMMED8(opcode, reg) \
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.at opcode; \
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rd_sel_source MICROCODE_RD_SEL, rd_sel reg, \
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alu_op SELB, b_sel IMMEDIATE, width W8, next_instruction;
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MOV_REG_IMMED8(0xb0, AL)
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MOV_REG_IMMED8(0xb1, CL)
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MOV_REG_IMMED8(0xb2, DL)
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MOV_REG_IMMED8(0xb3, BL)
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MOV_REG_IMMED8(0xb4, AH)
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MOV_REG_IMMED8(0xb5, CH)
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MOV_REG_IMMED8(0xb6, DH)
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MOV_REG_IMMED8(0xb7, BH)
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#define MOV_REG_IMMED16(opcode, reg) \
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.at opcode; \
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rd_sel_source MICROCODE_RD_SEL, rd_sel reg, \
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alu_op SELB, b_sel IMMEDIATE, next_instruction;
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MOV_REG_IMMED16(0xb8, AX)
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MOV_REG_IMMED16(0xb9, CX)
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MOV_REG_IMMED16(0xba, DX)
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MOV_REG_IMMED16(0xbb, BX)
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MOV_REG_IMMED16(0xbc, SP)
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MOV_REG_IMMED16(0xbd, BP)
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MOV_REG_IMMED16(0xbe, SI)
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MOV_REG_IMMED16(0xbf, DI)
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// MOV 0xa0 al := m[immed16]
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.at 0xa0;
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mar_write, mar_wr_sel Q, b_sel IMMEDIATE, alu_op SELB, jmp mova0, segment DS;
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// MOV 0xa1 ax := m[immed16]
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.at 0xa1;
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mar_write, mar_wr_sel Q, b_sel IMMEDIATE, alu_op SELB, jmp mova0, segment DS;
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.auto_address;
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mova0:
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segment DS, width WAUTO, mem_read;
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rd_sel_source MICROCODE_RD_SEL, rd_sel AL, width WAUTO,
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a_sel MDR, alu_op SELA, next_instruction;
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// MOV 0xa2 m[immed16] := al
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.at 0xa2;
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mar_write, mar_wr_sel Q, b_sel IMMEDIATE, alu_op SELB, jmp mova2, ra_sel AL;
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.at 0xa3;
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mar_write, mar_wr_sel Q, b_sel IMMEDIATE, alu_op SELB, jmp mova2, ra_sel AL;
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.auto_address;
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mova2:
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a_sel RA, alu_op SELA, mdr_write, segment DS, jmp write_complete;
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// MOV 0x8e sr := reg/mem
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.at 0x8e;
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mar_write, mar_wr_sel EA, ra_modrm_rm_reg,
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segment DS, jmp_rm_reg_mem mov8e_reg;
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.auto_address;
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mov8e_reg:
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segment_wr_en, rd_sel_source MODRM_REG, a_sel RA, alu_op SELA,
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ext_int_inhibit, next_instruction;
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mov8e_mem:
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segment DS, mem_read;
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rd_sel_source MODRM_REG, segment_wr_en, a_sel MDR, alu_op SELA,
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ext_int_inhibit, next_instruction;
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// MOV 0x8c reg/mem := sr
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.at 0x8c;
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mar_write, mar_wr_sel EA, jmp_dispatch_reg dispatch_8c;
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.auto_address;
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dispatch_8c:
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segment_force, segment ES, jmp_rm_reg_mem mov8c_reg;
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segment_force, segment CS, jmp_rm_reg_mem mov8c_reg;
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segment_force, segment SS, jmp_rm_reg_mem mov8c_reg;
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segment_force, segment DS, jmp_rm_reg_mem mov8c_reg;
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segment_force, segment ES, jmp_rm_reg_mem mov8c_reg;
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segment_force, segment CS, jmp_rm_reg_mem mov8c_reg;
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segment_force, segment SS, jmp_rm_reg_mem mov8c_reg;
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segment_force, segment DS, jmp_rm_reg_mem mov8c_reg;
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mov8c_reg:
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rd_sel_source MODRM_RM_REG, b_sel SR, alu_op SELB,
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next_instruction;
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mov8c_mem:
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b_sel SR, alu_op SELB, mdr_write, segment DS, jmp write_16_complete;
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