mirror of
https://github.com/Gehstock/Mist_FPGA.git
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83 lines
1.7 KiB
VHDL
83 lines
1.7 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.all;
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ENTITY sprom IS
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GENERIC
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(
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init_file : string := "";
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widthad_a : natural;
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width_a : natural := 8;
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outdata_reg_a : string := "UNREGISTERED"
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);
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PORT
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(
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address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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clock : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
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);
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END sprom;
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ARCHITECTURE SYN OF sprom IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
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COMPONENT altsyncram
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GENERIC (
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address_aclr_a : STRING;
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clock_enable_input_a : STRING;
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clock_enable_output_a : STRING;
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init_file : STRING;
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intended_device_family : STRING;
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lpm_hint : STRING;
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lpm_type : STRING;
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numwords_a : NATURAL;
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operation_mode : STRING;
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outdata_aclr_a : STRING;
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outdata_reg_a : STRING;
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widthad_a : NATURAL;
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width_a : NATURAL;
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width_byteena_a : NATURAL
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);
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PORT (
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clock0 : IN STD_LOGIC ;
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address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
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q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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q <= sub_wire0(width_a-1 DOWNTO 0);
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altsyncram_component : altsyncram
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GENERIC MAP (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => init_file,
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intended_device_family => "Cyclone III",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 2**widthad_a,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => outdata_reg_a,
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widthad_a => widthad_a,
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width_a => width_a,
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width_byteena_a => 1
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)
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PORT MAP (
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clock0 => clock,
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address_a => address,
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q_a => sub_wire0
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);
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END SYN;
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