mirror of
https://github.com/Gehstock/Mist_FPGA.git
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220 lines
7.6 KiB
VHDL
220 lines
7.6 KiB
VHDL
------------------------------------------------------------------------------
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-- Project : Red Zombie
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------------------------------------------------------------------------------
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-- File : redzombie.vhd
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-- Author : fpgakuechle
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-- Company : hobbyist
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-- Created : 2012-12
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-- Last update: 2013-04-02
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-- Lizenz : GNU General Public License (http://www.gnu.de/documents/gpl.de.html)
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------------------------------------------------------------------------------
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-- Description:
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--parallel io unit
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--Zilog Z80 PIO - U855
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------------------------------------------------------------------------------
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--Status: UNDER CONSTRUCTION: 2013-03-03
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--missing: IRQ-control
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--control register/data path under test now
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--last change: fixed: mixed up mask and mode register; add single bit mode
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-- fixed: outputs *_rdy at single bit mode
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity pio is
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port(
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clk : in std_logic;
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ce_ni : in std_logic;
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IOREQn_i : in std_logic;
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data_o : out std_logic_vector(7 downto 0);
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data_i : in std_logic_vector(7 downto 0);
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RD_n : in std_logic;
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M1_n : in std_logic;
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sel_b_nA : in std_logic;
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sel_c_nD : in std_logic;
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--
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IRQEna_i : in std_logic;
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IRQEna_o : out std_logic;
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INTn_o : out std_logic;
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astb_n : in std_logic; --Data strobe in, is able to generate IREQ
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ardy_n : out std_logic; --
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porta_o : out std_logic_vector(7 downto 0);
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porta_i : in std_logic_vector(7 downto 0);
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bstb_n : in std_logic;
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brdy_n : out std_logic;
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portb_o : out std_logic_vector(7 downto 0);
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portb_i : in std_logic_vector(7 downto 0));
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end entity pio;
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architecture behave of pio is
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signal ctrl_selected : boolean;
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signal data_selected : boolean;
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type T_ALL_REGS_INDEX is (
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IRQ_VEC, MODE, PORTDIR, IRQ_CTRL, MASK, ERR);
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type T_PORT_INDEX is (PORT_A, PORT_B);
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subtype T_REG is std_logic_vector(7 downto 0);
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type T_ALL_REGS is array (T_ALL_REGS_INDEX) of T_REG;
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signal reg_index : T_ALL_REGS_INDEX;
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type T_2P_SL is array (T_PORT_INDEX'left to T_PORT_INDEX'right) of std_logic;
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type T_2P_REG_7b is array (T_PORT_INDEX) of std_logic_vector(7 downto 1);
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type T_2P_REG_8b is array (T_PORT_INDEX) of std_logic_vector(7 downto 0);
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type T_2P_REG_2b is array (T_PORT_INDEX) of std_logic_vector(7 downto 6);
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--default mode: Byte - Out
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signal mode_reg : T_2P_REG_2b := (others => "01");
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signal portdir_reg : T_2P_REG_8b := (others => x"00");
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signal mask_reg : T_2P_REG_8b := (others => x"00");
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signal irq_vec_reg : T_2P_REG_7b := (others => "0000000");
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signal irq_ctrl_reg : std_logic_vector(7 downto 4) := (others => '0');
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signal err_reg : std_logic_vector(7 downto 0) := (others => '0');
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signal wr_dir_reg_q : boolean := false;
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signal wr_mask_reg_q : boolean := false;
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signal data_oq : std_logic_vector(7 downto 0);
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signal port_sel : T_PORT_INDEX;
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--ports as vectors
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signal port_indata : T_2P_REG_8b;
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signal port_outdata : T_2P_REG_8b;
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--ports regs
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signal port_indata_reg : T_2P_REG_8b;
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signal port_outdata_reg : T_2P_REG_8b;
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signal strb_in : T_2P_SL;
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signal rdy_out : T_2P_SL;
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begin
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port_sel <= PORT_B when sel_b_nA = '1' else
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PORT_A;
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strb_in(PORT_A) <= astb_n;
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strb_in(PORT_B) <= bstb_n;
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ardy_n <= rdy_out(PORT_A);
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brdy_n <= rdy_out(PORT_B);
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port_indata(PORT_A) <= porta_i;
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port_indata(PORT_B) <= portb_i;
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porta_o <= port_outdata(PORT_A);
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portb_o <= port_outdata(PORT_B);
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--built enables for control register
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process(data_i(3 downto 0), wr_dir_reg_q, wr_mask_reg_q) is
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begin
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if wr_dir_reg_q then
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reg_index <= PORTDIR;
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elsif wr_mask_reg_q then
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reg_index <= MASK;
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elsif data_i(0) = '0' then
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reg_index <= IRQ_VEC;
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elsif data_i(3 downto 0) = x"F" then
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reg_index <= MODE;
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elsif data_i(3 downto 0) = x"7" then
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reg_index <= IRQ_CTRL;
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else
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reg_index <= ERR;
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end if;
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end process;
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ctrl_selected <= ce_ni = '0' and IOREQn_i = '0' and sel_c_nD = '1'; --access controlregs
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data_selected <= ce_ni = '0' and IOREQn_i = '0' and sel_c_nD = '0'; --access ports
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--read/write control register
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process(clk)
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begin
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if falling_edge(clk) then
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if ctrl_selected then
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if rd_n = '1' then
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wr_dir_reg_q <= false;
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wr_mask_reg_q <= false;
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--write control reg
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case reg_index is
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when IRQ_VEC => irq_vec_reg(port_sel) <= data_i(7 downto 1);
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when MODE => mode_reg(port_sel) <= data_i(7 downto 6);
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if data_i(7 downto 6) = "11" then
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wr_dir_reg_q <= true;
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end if;
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when PORTDIR => portdir_reg(port_sel) <= data_i(7 downto 0);
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when IRQ_CTRL => irq_ctrl_reg <= data_i(7 downto 4);
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if data_i(4) = '1' then
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wr_mask_reg_q <= true;
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end if;
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when MASK => mask_reg(port_sel) <= data_i(7 downto 0);
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when ERR => err_reg <= data_i(7 downto 0);
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when others => err_reg <= data_i(7 downto 0);
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end case;
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else
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--read control reg ?How to select control register while reading?
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case reg_index is
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when IRQ_VEC => data_oq <= irq_vec_reg(port_sel) & '0';
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when MODE => data_oq <= mode_reg(port_sel) & "000000";
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when PORTDIR => data_oq <= portdir_reg(port_sel);
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when IRQ_CTRL => data_oq <= irq_ctrl_reg & x"0";
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when MASK => data_oq <= mask_reg(port_sel);
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when ERR => data_oq <= err_reg;
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when others => data_oq <= x"00";
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end case;
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end if;
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--port_regs <> CPU
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elsif data_selected then
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if rd_n = '0' then
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data_oq <= port_indata_reg(port_sel);
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else
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port_outdata_reg(port_sel) <= data_i;
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end if;
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end if;
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end if;
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end process;
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g_portCPU : for pchan in T_PORT_INDEX generate
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--real port access
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process(clk)
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begin
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if falling_edge(clk) then
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if mode_reg(pchan) = "00" then --output mode
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port_outdata(pchan) <= port_outdata_reg(pchan);
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elsif mode_reg(pchan) = "01" then --input mode
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port_indata_reg(pchan) <= port_indata(pchan);
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elsif mode_reg(pchan) = "10" then --bidir
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for i in 0 to 7 loop --strb contrl mot implemented yet
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if portdir_reg(pchan)(i) = '0' then --output
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port_outdata(pchan)(i) <= port_outdata_reg(pchan)(i);
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else
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port_indata_reg(pchan)(i) <= port_indata(pchan)(i);
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end if;
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end loop;
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elsif mode_reg(pchan) = "11" then --bit mode
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for i in 0 to 7 loop
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if portdir_reg(pchan)(i) = '0' then --output port
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port_outdata(pchan)(i) <= port_outdata_reg(pchan)(i);
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else --input port
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port_indata_reg(pchan)(i) <= port_indata(pchan)(i);
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end if;
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end loop;
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end if;
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end if;
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end process;
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end generate g_portCPU;
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data_o <= data_oq;
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--unused output yet
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IRQEna_o <= '1';
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INTn_o <= '1';
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rdy_out(PORT_A) <= '0' when mode_reg(PORT_A) = "11" else '1'; --other modes
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--not implemented
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rdy_out(PORT_B) <= '0' when mode_reg(PORT_B) = "11" and mode_reg(PORT_A) /= "10" else '1';
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end architecture;
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