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49 lines
1.3 KiB
VHDL
49 lines
1.3 KiB
VHDL
-- -----------------------------------------------------------------------
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--
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-- FPGA 64
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--
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-- A fully functional commodore 64 implementation in a single FPGA
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--
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-- -----------------------------------------------------------------------
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-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
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-- http://www.syntiac.com/fpga64.html
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-- -----------------------------------------------------------------------
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--
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-- Interface to 6502/6510 core
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--
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-- -----------------------------------------------------------------------
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library IEEE;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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-- -----------------------------------------------------------------------
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entity cpu65xx is
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generic (
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pipelineOpcode : boolean;
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pipelineAluMux : boolean;
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pipelineAluOut : boolean
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);
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port (
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clk : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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nmi_n : in std_logic;
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nmi_ack : out std_logic;
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irq_n : in std_logic;
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so_n : in std_logic := '1';
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di : in unsigned(7 downto 0);
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do : out unsigned(7 downto 0);
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addr : out unsigned(15 downto 0);
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we : out std_logic;
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debugOpcode : out unsigned(7 downto 0);
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debugPc : out unsigned(15 downto 0);
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debugA : out unsigned(7 downto 0);
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debugX : out unsigned(7 downto 0);
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debugY : out unsigned(7 downto 0);
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debugS : out unsigned(7 downto 0)
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);
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end cpu65xx; |