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https://github.com/Gehstock/Mist_FPGA.git
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79 lines
2.9 KiB
VHDL
79 lines
2.9 KiB
VHDL
--
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-- memmap.vhd
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--
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-- Manage offset for read ula
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--
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-- Copyright (C)2001 - 2005 SEILEBOST
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-- All rights reserved.
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--
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-- $Id: memmap.vhd, v0.02 2005/01/01 00:00:00 SEILEBOST $
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--
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-- TODO :
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-- Remark :
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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--use IEEE.std_logic_arith.all;
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--use IEEE.numeric_std.all;
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entity memmap is
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port ( TXTHIR_SEL : in std_logic;
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DBLHGT_SEL : in std_logic;
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FORCETXT : in std_logic;
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CPT_H : in std_logic_vector(6 downto 0);
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CPT_V : in std_logic_vector(8 downto 0);
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VAP1 : out std_logic_vector(15 downto 0);
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CHROWCNT : out std_logic_vector(2 downto 0);
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TXTHIR_DEC : out std_logic
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);
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end entity memmap;
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architecture memmap_arch of memmap is
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signal lDBLHGT_EN : std_logic; -- ENABLE DOUBLE HEIGT
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signal lTXTHIR_DEC : std_logic; -- MODE TEXT / HIRES
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signal lCPT_V_TMP : std_logic_vector(8 downto 0); -- VERTICAL COUNTER
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signal lCPT_V_8_TMP : std_logic_vector(8 downto 0); -- VERTICAL COUNTER DIVIDE OR NOT BY 8
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signal lVAP1 : std_logic_vector(12 downto 0); -- VIDEO ADDRESS PHASE 1
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signal lOFFSCR : std_logic_vector(15 downto 0); -- OFFSET SCREEN
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signal ltmpBy10 : std_logic_vector(12 downto 0); -- Using to mult by 10
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begin
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-- local signal
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lTXTHIR_DEC <= (TXTHIR_SEL and FORCETXT);
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lDBLHGT_EN <= (DBLHGT_SEL and lTXTHIR_DEC);
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-- Compute video adress phase 1
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lCPT_V_TMP <= '0'&CPT_V(8 downto 1) when lDBLHGT_EN = '1' else CPT_V(8 downto 0);
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-- divide by 8 if necessary : erreur sur la manière de diviser par 8? 03/02/2010
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--lCPT_V_8_TMP <= lCPT_V_TMP when lTXTHIR_DEC = '1' else lCPT_V_TMP(8 downto 3) & "000";
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lCPT_V_8_TMP <= lCPT_V_TMP when lTXTHIR_DEC = '1' else "000" & lCPT_V_TMP(8 downto 3) ;
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-- 03/02/2010 : Le bonne blague : après la phase de synthese, le 'bench' ne
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-- fonctionnait plus. Le synthetiseur de XILINX avait utilisé un multiplieur 18x18
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-- pour générer la multiplication par 10 et la simulation a repris cela. Or le
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-- multiplier a une latence de 1 µs (latence de l'horloge PHI2) d'où les problèmes
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-- durant les simulations (génération de 2 fois de suite de l'adresse vidéo)
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-- On revient à la bonne vieille méthode Bx10 = Bx8 + Bx2 !!
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--lVAP1 <= ("0000000" & CPT_H) + (lCPT_V_8_TMP * "1010");
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ltmpBy10 <= ("0" & lCPT_V_8_TMP & "000") + ("000" & lCPT_V_8_TMP & "0");
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-- le décalage en Y : il faut multiplier par 40 donc 4 * ltmpBy10
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lVAP1 <= ("00000" & CPT_H) + (ltmpBy10(10 downto 0) & "00");
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lOFFSCR <= X"A000" when lTXTHIR_DEC = '1' else X"BB80";
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VAP1 <= ("000" & lVAP1) + lOFFSCR;
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-- Compute character row counter
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CHROWCNT <= CPT_V(2 downto 0) when lDBLHGT_EN = '1' else CPT_V(3 downto 1);
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-- Output signal for texte/hires mode decode
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TXTHIR_DEC <= lTXTHIR_DEC;
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end architecture memmap_arch;
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