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88 lines
1.1 KiB
Systemverilog
88 lines
1.1 KiB
Systemverilog
module HighResBoard(
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input [7:0] Din,
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output [7:0] Dout,
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input CS0_n,
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input CS1_n,
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input CS2_n,
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input WR_n,
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input Clk,
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output[10:0] VAin,
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output[10:0] VAout
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);
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wire [7:0] IC1_Aout, IC1_Bin;
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TTL74LS245 IC1(
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.OE(CS2_n),
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.DIR(1'b0),
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.Ain(Din),
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.Aout(Aout),
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.Bin(),
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.Bout(Dout)
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);
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LS245 IC1(
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.DIR(1'b0),
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.OE(CS2_n),
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.Ai(Din),
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.Bi(Bin),
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.Ao(Dout),
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.Bo(Bout)
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);
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TTL74LS373 IC2(
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.LE(CS0_n),
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.D({Din[4],Din[5],Din[6],1'b0,Din[3],Din[2],Din[1],Din[0]}),
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.OE_n(~CS2_n),//inverted test
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.Q()
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);
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TTL74LS373 IC3(
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.LE(CS1_n),
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.D({1'b0,1'b0,1'b0,1'b0,1'b0,Din[2],Din[1],Din[0]}),
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.OE_n(~CS2_n),//inverted test
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.Q()
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);
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wire [9:0]addr;
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wire ram_we = WR_n | CS2_n;
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wire [7:0]din;
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wire [7:0]out;
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spram #(
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.addr_width_g(10),
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.data_width_g(8))
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IC4(
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.clk_i(Clk),
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.we_i(ram_we),
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.addr_i(addr),
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.data_i(din),
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.data_o(out)
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);
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TTL74LS245 IC5(
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.OE(~VAin[10]),
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.DIR(1'b1),
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.Ain(),
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.Aout(),
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.Bin(),
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.Bout()
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);
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TTL74LS245 IC6(
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.OE(CS2_n),
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.DIR(1'b0),
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.Ain(),
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.Aout(),
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.Bin(),
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.Bout()
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);
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TTL74LS245 IC7(
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.OE(CS2_n),
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.DIR(1'b0),
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.Ain(),
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.Aout(),
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.Bin(),
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.Bout()
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);
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endmodule
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