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42 lines
1012 B
Verilog
42 lines
1012 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Paul Wightmore
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//
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// Create Date: 19:33:12 05/01/2018
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// Design Name: LS245
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// Module Name: system86\src\ttl\ls245.v
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// Project Name: Namco System86 simulation
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// Target Devices:
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// Tool versions:
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// Description: LS245 - Octal Bus Transceiver
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// License: https://www.apache.org/licenses/LICENSE-2.0
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//
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//////////////////////////////////////////////////////////////////////////////////
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module LS245(
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input wire DIR,
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input wire OE,
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input wire [7:0] Ai,
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input wire [7:0] Bi,
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output wire [7:0] Ao,
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output wire [7:0] Bo
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);
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wire BToA = OE & ~DIR;
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wire AToB = OE & DIR;
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assign Ao = BToA ? Bi : 8'bZ;
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assign Bo = AToB ? Ai : 8'bZ;
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// assign A = BToA ? B : 8'bZ;
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// assign B = AToB ? A : 8'bZ;
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endmodule
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