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https://github.com/Gehstock/Mist_FPGA.git
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173 lines
6.8 KiB
VHDL
173 lines
6.8 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Copyright (c) 2016, Fabio Belavenuto (belavenuto@gmail.com)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity dpSRAM_5128 is
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port (
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clk_i : in std_logic;
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-- Port 0
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porta0_addr_i : in std_logic_vector(18 downto 0);
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porta0_ce_i : in std_logic;
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porta0_oe_i : in std_logic;
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porta0_we_i : in std_logic;
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porta0_data_i : in std_logic_vector(7 downto 0);
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porta0_data_o : out std_logic_vector(7 downto 0);
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-- Port 1
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porta1_addr_i : in std_logic_vector(18 downto 0);
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porta1_ce_i : in std_logic;
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porta1_oe_i : in std_logic;
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porta1_we_i : in std_logic;
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porta1_data_i : in std_logic_vector(7 downto 0);
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porta1_data_o : out std_logic_vector(7 downto 0);
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-- SRAM in board
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sram_addr_o : out std_logic_vector(18 downto 0);
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sram_data_io : inout std_logic_vector(7 downto 0);
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sram_ce_n_o : out std_logic := '1';
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sram_oe_n_o : out std_logic := '1';
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sram_we_n_o : out std_logic := '1'
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);
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end entity;
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architecture Behavior of dpSRAM_5128 is
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signal sram_we_s : std_logic;
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signal sram_oe_s : std_logic;
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begin
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sram_ce_n_o <= '0'; -- sempre ativa
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sram_we_n_o <= sram_we_s;
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sram_oe_n_o <= sram_oe_s;
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process (clk_i)
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variable state_v : std_logic := '0';
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variable p0_ce_v : std_logic_vector(1 downto 0);
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variable p1_ce_v : std_logic_vector(1 downto 0);
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variable acesso0_v : std_logic;
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variable acesso1_v : std_logic;
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variable p0_req_v : std_logic := '0';
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variable p1_req_v : std_logic := '0';
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variable p0_we_v : std_logic := '0';
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variable p1_we_v : std_logic := '0';
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variable p0_addr_v : std_logic_vector(18 downto 0);
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variable p1_addr_v : std_logic_vector(18 downto 0);
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variable p0_data_v : std_logic_vector(7 downto 0);
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variable p1_data_v : std_logic_vector(7 downto 0);
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begin
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if rising_edge(clk_i) then
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acesso0_v := porta0_ce_i and (porta0_oe_i or porta0_we_i);
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acesso1_v := porta1_ce_i and (porta1_oe_i or porta1_we_i);
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p0_ce_v := p0_ce_v(0) & acesso0_v;
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p1_ce_v := p1_ce_v(0) & acesso1_v;
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if p0_ce_v = "01" then -- detecta rising edge do pedido da porta0
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p0_req_v := '1'; -- marca que porta0 pediu acesso
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p0_we_v := '0'; -- por enquanto eh leitura
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p0_addr_v := porta0_addr_i; -- pegamos endereco
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if porta0_we_i = '1' then -- se foi gravacao que a porta0 pediu
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p0_we_v := '1'; -- marcamos que eh gravacao
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p0_data_v := porta0_data_i; -- pegamos dado
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end if;
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end if;
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if p1_ce_v = "01" then -- detecta rising edge do pedido da porta1
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p1_req_v := '1'; -- marca que porta1 pediu acesso
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p1_we_v := '0'; -- por enquanto eh leitura
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p1_addr_v := porta1_addr_i; -- pegamos endereco
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if porta1_we_i = '1' then -- se foi gravacao que a porta1 pediu
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p1_we_v := '1'; -- marcamos que eh gravacao
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p1_data_v := porta1_data_i; -- pegamos dado
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end if;
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end if;
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if state_v = '0' then -- Estado 0
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sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
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if p0_req_v = '1' then -- pedido da porta0 pendente
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sram_addr_o <= p0_addr_v; -- colocamos o endereco pedido na SRAM
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sram_we_s <= '1';
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-- sram_ce_n <= '0';
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sram_oe_s <= '0';
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if p0_we_v = '1' then -- se for gravacao
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sram_data_io <= p0_data_v; -- damos o dado para a SRAM
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sram_we_s <= '0'; -- e dizemos para ela gravar
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sram_oe_s <= '1';
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end if;
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state_v := '1';
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elsif p1_req_v = '1' then -- pedido da porta1 pendente
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sram_addr_o <= p1_addr_v; -- colocamos o endereco pedido na SRAM
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sram_we_s <= '1';
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-- sram_ce_n <= '0';
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sram_oe_s <= '0';
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if p1_we_v = '1' then -- se for gravacao
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sram_data_io <= p1_data_v; -- damos o dado para a SRAM
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sram_we_s <= '0'; -- e dizemos para ela gravar
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sram_oe_s <= '1';
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end if;
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state_v := '1'; -- proximo rising do clock vamos para segundo estado
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end if;
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elsif state_v = '1' then -- Estado 1
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if p0_req_v = '1' then -- pedido da porta0 pendente
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sram_we_s <= '1';
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sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
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if p0_we_v = '0' then -- se for leitura
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porta0_data_o <= sram_data_io; -- pegamos o dado que a SRAM devolveu
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end if;
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p0_req_v := '0'; -- limpamos a flag de requisicao da porta0
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state_v := '0'; -- voltar para estado 0
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sram_oe_s <= '1';
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-- sram_ce_n <= '1';
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elsif p1_req_v = '1' then -- pedido da porta1 pendente
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sram_we_s <= '1';
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sram_data_io <= (others => 'Z'); -- desconectar bus da SRAM
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if p1_we_v = '0' then -- se for leitura
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porta1_data_o <= sram_data_io; -- pegamos o dado que a SRAM devolveu
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end if;
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p1_req_v := '0'; -- limpamos a flag de requisicao da porta1
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state_v := '0'; -- voltar para estado 0
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sram_oe_s <= '1';
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-- sram_ce_n <= '1';
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end if;
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end if;
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end if;
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end process;
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end; |