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37 lines
642 B
Verilog
37 lines
642 B
Verilog
module mist_audio
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(
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input clk,
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input reset_n,
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input [BITS-1:0] audio_inL,
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input [BITS-1:0] audio_inR,
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output AUDIO_L,
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output AUDIO_R
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);
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parameter BITS = 16;
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parameter STEREO = 0;
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parameter SIGNED = 0;
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wire [BITS-1:0] aud_left = ~SIGNED ? audio_inL : {~audio_inL[BITS-1],audio_inL[BITS-2:0]};
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wire [BITS-1:0] aud_right = STEREO ? ~SIGNED ? audio_inR : {~audio_inR[BITS-1],audio_inR[BITS-2:0]} : aud_left;
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dac #(
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.C_bits(BITS))
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dacl(
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.clk_i(clk),
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.res_n_i(reset_n),
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.dac_i(aud_left),
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.dac_o(AUDIO_L)
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);
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dac #(
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.C_bits(BITS))
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dacr(
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.clk_i(clk),
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.res_n_i(reset_n),
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.dac_i(aud_right),
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.dac_o(AUDIO_R)
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);
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endmodule
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