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171 lines
5.0 KiB
VHDL
171 lines
5.0 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- The Port 1 unit.
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-- Implements the Port 1 logic.
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--
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-- $Id: p1.vhd,v 1.4 2004/07/11 16:51:33 arniml Exp $
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t48_pack.word_t;
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entity p1 is
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port (
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-- Global Interface -------------------------------------------------------
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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-- T48 Bus Interface ------------------------------------------------------
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data_i : in word_t;
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data_o : out word_t;
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write_p1_i : in boolean;
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read_p1_i : in boolean;
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read_reg_i : in boolean;
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-- Port 1 Interface -------------------------------------------------------
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p1_i : in word_t;
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p1_o : out word_t;
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p1_low_imp_o : out std_logic
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);
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end p1;
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use work.t48_pack.clk_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.bus_idle_level_c;
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architecture rtl of p1 is
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-- the port output register
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signal p1_q : word_t;
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-- the low impedance marker
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signal low_imp_q : std_logic;
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begin
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-----------------------------------------------------------------------------
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-- Process p1_reg
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--
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-- Purpose:
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-- Implements the port output register.
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--
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p1_reg: process (res_i, clk_i)
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begin
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if res_i = res_active_c then
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p1_q <= (others => '1');
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low_imp_q <= '0';
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elsif clk_i'event and clk_i = clk_active_c then
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if en_clk_i then
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if write_p1_i then
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p1_q <= data_i;
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low_imp_q <= '1';
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else
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low_imp_q <= '0';
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end if;
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end if;
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end if;
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end process p1_reg;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process p1_data
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--
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-- Purpose:
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-- Generates the T48 bus data.
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--
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p1_data: process (read_p1_i,
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p1_i,
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read_reg_i,
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p1_q)
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begin
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data_o <= (others => bus_idle_level_c);
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if read_p1_i then
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if read_reg_i then
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data_o <= p1_q;
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else
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data_o <= p1_i;
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end if;
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end if;
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end process p1_data;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output Mapping.
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-----------------------------------------------------------------------------
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p1_o <= p1_q;
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p1_low_imp_o <= low_imp_q;
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end rtl;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: p1.vhd,v $
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-- Revision 1.4 2004/07/11 16:51:33 arniml
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-- cleanup copyright notice
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--
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-- Revision 1.3 2004/05/17 14:37:53 arniml
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-- reorder data_o generation
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--
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-- Revision 1.2 2004/03/29 19:39:58 arniml
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-- rename pX_limp to pX_low_imp
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--
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- initial check-in
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--
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-------------------------------------------------------------------------------
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