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241 lines
7.1 KiB
VHDL
241 lines
7.1 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- The Program Status Word (PSW).
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-- Implements the PSW with its special bits.
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--
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-- $Id: psw.vhd,v 1.7 2004/07/11 16:51:33 arniml Exp $
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t48_pack.word_t;
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entity psw is
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port (
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-- Global Interface -------------------------------------------------------
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clk_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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-- T48 Bus Interface ------------------------------------------------------
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data_i : in word_t;
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data_o : out word_t;
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read_psw_i : in boolean;
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read_sp_i : in boolean;
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write_psw_i : in boolean;
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write_sp_i : in boolean;
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-- Decoder Interface ------------------------------------------------------
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special_data_i : in std_logic;
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inc_stackp_i : in boolean;
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dec_stackp_i : in boolean;
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write_carry_i : in boolean;
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write_aux_carry_i : in boolean;
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write_f0_i : in boolean;
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write_bs_i : in boolean;
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carry_o : out std_logic;
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aux_carry_i : in std_logic;
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aux_carry_o : out std_logic;
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f0_o : out std_logic;
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bs_o : out std_logic
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);
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end psw;
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library ieee;
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use ieee.numeric_std.all;
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use work.t48_pack.clk_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.nibble_t;
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architecture rtl of psw is
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-- special bit positions in PSW
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constant carry_c : natural := 3;
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constant aux_carry_c : natural := 2;
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constant f0_c : natural := 1;
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constant bs_c : natural := 0;
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-- the PSW register
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signal psw_q : nibble_t;
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-- the Stack Pointer
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signal sp_q : unsigned(2 downto 0);
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-- pragma translate_off
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signal psw_s : word_t;
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-- pragma translate_on
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begin
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-----------------------------------------------------------------------------
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-- Process psw_reg
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--
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-- Purpose:
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-- Implements the PSW register.
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--
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psw_reg: process (res_i, clk_i)
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begin
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if res_i = res_active_c then
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psw_q <= (others => '0');
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sp_q <= (others => '0');
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elsif clk_i'event and clk_i = clk_active_c then
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if en_clk_i then
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-- T48 bus access
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if write_psw_i then
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psw_q <= data_i(7 downto 4);
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end if;
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if write_sp_i then
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sp_q <= unsigned(data_i(2 downto 0));
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end if;
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-- increment Stack Pointer
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if inc_stackp_i then
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sp_q <= sp_q + 1;
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end if;
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-- decrement Stack Pointer
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if dec_stackp_i then
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sp_q <= sp_q - 1;
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end if;
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-- access to special bits
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if write_carry_i then
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psw_q(carry_c) <= special_data_i;
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end if;
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--
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if write_aux_carry_i then
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psw_q(aux_carry_c) <= aux_carry_i;
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end if;
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--
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if write_f0_i then
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psw_q(f0_c) <= special_data_i;
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end if;
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--
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if write_bs_i then
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psw_q(bs_c) <= special_data_i;
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end if;
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end if;
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end if;
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end process psw_reg;
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process data_out
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--
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-- Purpose:
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-- Output multiplexer for T48 Data Bus.
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--
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data_out: process (read_psw_i,
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read_sp_i,
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psw_q,
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sp_q)
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begin
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data_o <= (others => bus_idle_level_c);
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if read_psw_i then
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data_o(7 downto 4) <= psw_q;
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end if;
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if read_sp_i then
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data_o(3 downto 0) <= '1' & std_logic_vector(sp_q);
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end if;
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end process data_out;
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--
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-----------------------------------------------------------------------------
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-- pragma translate_off
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tb: process (psw_q, sp_q)
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begin
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psw_s(7 downto 4) <= psw_q;
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psw_s(3) <= '1';
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psw_s(2 downto 0) <= std_logic_vector(sp_q);
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end process tb;
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-- pragma translate_on
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-----------------------------------------------------------------------------
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-- Output mapping.
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-----------------------------------------------------------------------------
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carry_o <= psw_q(carry_c);
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aux_carry_o <= psw_q(aux_carry_c);
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f0_o <= psw_q(f0_c);
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bs_o <= psw_q(bs_c);
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end rtl;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: psw.vhd,v $
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-- Revision 1.7 2004/07/11 16:51:33 arniml
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-- cleanup copyright notice
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--
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-- Revision 1.6 2004/04/24 23:44:25 arniml
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-- move from std_logic_arith to numeric_std
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--
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-- Revision 1.5 2004/04/24 11:25:39 arniml
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-- removed dummy_s - workaround not longer needed for GHDL 0.11.1
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--
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-- Revision 1.4 2004/04/18 18:59:01 arniml
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-- add temporary workaround for GHDL 0.11
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--
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-- Revision 1.3 2004/04/04 14:15:45 arniml
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-- add dump_compare support
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--
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-- Revision 1.2 2004/03/28 21:28:13 arniml
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-- take auxiliary carry from direct ALU connection
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--
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-- Revision 1.1 2004/03/23 21:31:53 arniml
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-- initial check-in
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--
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-------------------------------------------------------------------------------
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