mirror of
https://github.com/Gehstock/Mist_FPGA.git
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208 lines
9.8 KiB
Plaintext
208 lines
9.8 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2014 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
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# Date created = 18:01:06 September 29, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# asteroids_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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# Pin & Location Assignments
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# ==========================
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set_location_assignment PIN_7 -to LED
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set_location_assignment PIN_54 -to CLOCK_27
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set_location_assignment PIN_144 -to VGA_R[5]
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set_location_assignment PIN_143 -to VGA_R[4]
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set_location_assignment PIN_142 -to VGA_R[3]
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set_location_assignment PIN_141 -to VGA_R[2]
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set_location_assignment PIN_137 -to VGA_R[1]
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set_location_assignment PIN_135 -to VGA_R[0]
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set_location_assignment PIN_133 -to VGA_B[5]
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set_location_assignment PIN_132 -to VGA_B[4]
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set_location_assignment PIN_125 -to VGA_B[3]
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set_location_assignment PIN_121 -to VGA_B[2]
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set_location_assignment PIN_120 -to VGA_B[1]
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set_location_assignment PIN_115 -to VGA_B[0]
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set_location_assignment PIN_114 -to VGA_G[5]
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set_location_assignment PIN_113 -to VGA_G[4]
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set_location_assignment PIN_112 -to VGA_G[3]
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set_location_assignment PIN_111 -to VGA_G[2]
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set_location_assignment PIN_110 -to VGA_G[1]
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set_location_assignment PIN_106 -to VGA_G[0]
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set_location_assignment PIN_136 -to VGA_VS
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set_location_assignment PIN_119 -to VGA_HS
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set_location_assignment PIN_65 -to AUDIO_L
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set_location_assignment PIN_80 -to AUDIO_R
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set_location_assignment PIN_105 -to SPI_DO
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set_location_assignment PIN_88 -to SPI_DI
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set_location_assignment PIN_126 -to SPI_SCK
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set_location_assignment PIN_127 -to SPI_SS2
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set_location_assignment PIN_91 -to SPI_SS3
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set_location_assignment PIN_13 -to CONF_DATA0
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# Classic Timing Assignments
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# ==========================
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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# Analysis & Synthesis Assignments
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# ================================
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name SEARCH_PATH device/cycloneii/ -tag from_archive
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set_global_assignment -name SEARCH_PATH src/component/ps2/ -tag from_archive
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set_global_assignment -name SEARCH_PATH src/pace/ -tag from_archive
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set_global_assignment -name SEARCH_PATH src/pace/stubs/ -tag from_archive
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set_global_assignment -name SEARCH_PATH src/pace/video/ -tag from_archive
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set_global_assignment -name SEARCH_PATH src/platform/asteroids/ -tag from_archive
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set_global_assignment -name SEARCH_PATH src/platform/asteroids/roms/ -tag from_archive
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set_global_assignment -name SEARCH_PATH src/platform/asteroids/unzip/source/ -tag from_archive
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set_global_assignment -name SEARCH_PATH src/target/mist/ -tag from_archive
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set_global_assignment -name TOP_LEVEL_ENTITY Asteroid_MiST
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set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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# Fitter Assignments
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# ==================
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set_global_assignment -name DEVICE EP3C25E144C8
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
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set_global_assignment -name SEED 1
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set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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set_global_assignment -name ENABLE_NCE_PIN OFF
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set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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# Assembler Assignments
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# =====================
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set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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set_global_assignment -name GENERATE_RBF_FILE ON
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# Power Estimation Assignments
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# ============================
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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# Advanced I/O Timing Assignments
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# ===============================
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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# ------------------------
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# start ENTITY(target_top)
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# start LOGICLOCK_REGION(Root Region)
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# -----------------------------------
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# LogicLock Region Assignments
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# ============================
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# end LOGICLOCK_REGION(Root Region)
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# ---------------------------------
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# start DESIGN_PARTITION(Top)
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# ---------------------------
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# Incremental Compilation Assignments
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# ===================================
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# end DESIGN_PARTITION(Top)
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# -------------------------
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# end ENTITY(target_top)
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# ----------------------
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/Asteroid_MiST.sv
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set_global_assignment -name VHDL_FILE rtl/target_top.vhd
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set_global_assignment -name VHDL_FILE rtl/asteroids.vhd
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set_global_assignment -name VHDL_FILE rtl/asteroids_vg.vhd
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set_global_assignment -name VHDL_FILE rtl/asteroids_ram.vhd
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set_global_assignment -name VHDL_FILE rtl/asteroids_pokey.vhd
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set_global_assignment -name VHDL_FILE rtl/platform_pkg.vhd
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set_global_assignment -name VHDL_FILE rtl/pkg_asteroids_xilinx_prims.vhd
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set_global_assignment -name VHDL_FILE rtl/pkg_asteroids.vhd
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set_global_assignment -name VHDL_FILE rtl/wrappers.vhd
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set_global_assignment -name VHDL_FILE rtl/video_mixer.vhd
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set_global_assignment -name VHDL_FILE rtl/video_controller_pkg_body.vhd
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set_global_assignment -name VHDL_FILE rtl/video_controller_pkg.vhd
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set_global_assignment -name VHDL_FILE rtl/video_controller.vhd
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set_global_assignment -name VHDL_FILE rtl/tilemapctl_e.vhd
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set_global_assignment -name VHDL_FILE rtl/sprom.vhd
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set_global_assignment -name VHDL_FILE rtl/sprite_pkg_body.vhd
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set_global_assignment -name VHDL_FILE rtl/sprite_pkg.vhd
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set_global_assignment -name VHDL_FILE rtl/spram.vhd
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set_global_assignment -name VHDL_FILE rtl/project_pkg.vhd
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set_global_assignment -name VHDL_FILE rtl/pllclk_ez.vhd
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set_global_assignment -name VHDL_FILE rtl/pace_pkg_body.vhd
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set_global_assignment -name VHDL_FILE rtl/pace_pkg.vhd
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set_global_assignment -name VHDL_FILE rtl/pace.vhd
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set_global_assignment -name VHDL_FILE rtl/Graphics.VHD
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set_global_assignment -name VHDL_FILE rtl/dpram.vhd
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set_global_assignment -name VHDL_FILE rtl/custom_io.vhd
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set_global_assignment -name VHDL_FILE rtl/bitmapctl_e.vhd
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set_global_assignment -name VHDL_FILE rtl/bitmapctl.vhd
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set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
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set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
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set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
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set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
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set_global_assignment -name VHDL_FILE rtl/roms/prog_rom_0.vhd
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set_global_assignment -name VHDL_FILE rtl/roms/prog_rom_1.vhd
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set_global_assignment -name VHDL_FILE rtl/roms/prog_rom_2.vhd
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set_global_assignment -name VHDL_FILE rtl/roms/vec_rom_1.vhd
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set_global_assignment -name VHDL_FILE rtl/roms/dvg_rom_1.vhd
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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set_global_assignment -name VERILOG_FILE rtl/pll.v
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |