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https://github.com/Gehstock/Mist_FPGA.git
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79 lines
1.5 KiB
Verilog
79 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 08:11:34 09/23/2016
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// Design Name:
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// Module Name: mc6809e
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module mc6809(
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input [7:0] D,
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output [7:0] DOut,
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output [15:0] ADDR,
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output RnW,
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output E,
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output Q,
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output BS,
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output BA,
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input nIRQ,
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input nFIRQ,
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input nNMI,
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input EXTAL,
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input XTAL,
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input nHALT,
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input nRESET,
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input MRDY,
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input nDMABREQ,
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output [111:0] RegData
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);
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reg [1:0] clk_phase=2'b00;
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wire CLK;
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assign CLK=EXTAL;
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wire LIC;
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wire BUSY;
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wire AVMA;
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reg rE;
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reg rQ;
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assign E = rE;
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assign Q = rQ;
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mc6809i cpucore(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ),
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.nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(nDMABREQ)
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,.RegData(RegData)
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);
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always @(negedge CLK)
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begin
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case (clk_phase)
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2'b00:
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rE <= 0;
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2'b01:
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rQ <= 1;
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2'b10:
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rE <= 1;
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2'b11:
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rQ <= 0;
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endcase
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if (MRDY == 1'b1)
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clk_phase <= clk_phase + 2'b01;
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end
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endmodule
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