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49 lines
1.0 KiB
Verilog
49 lines
1.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 08:11:34 09/23/2016
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// Design Name:
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// Module Name: mc6809e
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module mc6809e(
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input [7:0] D,
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output [7:0] DOut,
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output [15:0] ADDR,
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output RnW,
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input E,
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input Q,
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output BS,
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output BA,
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input nIRQ,
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input nFIRQ,
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input nNMI,
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output AVMA,
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output BUSY,
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output LIC,
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input nHALT,
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input nRESET
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);
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mc6809i cpucore (.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ),
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.nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(1)
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);
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endmodule
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