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304 lines
8.1 KiB
Verilog
304 lines
8.1 KiB
Verilog
/* This file is part of JT51.
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JT51 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT51 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT51. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-10-2016
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*/
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`timescale 1ns / 1ps
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module jt51_reg(
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input rst,
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input clk,
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input cen, // P1
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input [7:0] din,
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input up_rl,
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input up_kc,
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input up_kf,
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input up_pms,
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input up_dt1,
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input up_tl,
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input up_ks,
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input up_amsen,
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input up_dt2,
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input up_d1l,
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input up_keyon,
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input [1:0] op, // operator to update
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input [2:0] ch, // channel to update
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input csm,
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input overflow_A,
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output reg busy,
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output [1:0] rl_I,
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output [2:0] fb_II,
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output [2:0] con_I,
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output [6:0] kc_I,
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output [5:0] kf_I,
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output [2:0] pms_I,
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output [1:0] ams_VII,
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output [2:0] dt1_II,
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output [3:0] mul_VI,
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output [6:0] tl_VII,
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output [1:0] ks_III,
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output amsen_VII,
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output [4:0] arate_II,
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output [4:0] rate1_II,
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output [4:0] rate2_II,
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output [3:0] rrate_II,
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output [1:0] dt2_I,
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output [3:0] d1l_I,
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output keyon_II,
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// Pipeline order
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output reg zero,
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output reg m1_enters,
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output reg m2_enters,
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output reg c1_enters,
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output reg c2_enters,
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// Operator
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output use_prevprev1,
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output use_internal_x,
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output use_internal_y,
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output use_prev2,
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output use_prev1,
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output [1:0] cur_op,
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output reg op31_no,
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output reg op31_acc
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);
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reg kon, koff;
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reg [1:0] csm_state;
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reg [4:0] csm_cnt;
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wire csm_kon = csm_state[0];
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wire csm_koff = csm_state[1];
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always @(*) begin
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m1_enters = cur_op == 2'b00;
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m2_enters = cur_op == 2'b01;
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c1_enters = cur_op == 2'b10;
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c2_enters = cur_op == 2'b11;
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end
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wire up = up_rl | up_kc | up_kf | up_pms | up_dt1 | up_tl |
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up_ks | up_amsen | up_dt2 | up_d1l | up_keyon;
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reg [4:0] cur;
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always @(posedge clk) if(cen) begin
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op31_no <= cur == 5'o10;
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op31_acc <= cur == 5'o16;
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end
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assign cur_op = cur[4:3];
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wire [4:0] req_I = { op, ch };
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wire [4:0] req_II = req_I + 5'd1;
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wire [4:0] req_III = req_II + 5'd1;
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wire [4:0] req_IV = req_III + 5'd1;
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wire [4:0] req_V = req_IV + 5'd1;
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wire [4:0] req_VI = req_V + 5'd1;
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wire [4:0] req_VII = req_VI + 5'd1;
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wire update_op_I = cur == req_I;
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wire update_op_II = cur == req_II;
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wire update_op_III = cur == req_III;
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wire update_op_IV = cur == req_IV;
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wire update_op_V = cur == req_V;
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wire update_op_VI = cur == req_VI;
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wire update_op_VII = cur == req_VII;
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wire up_rl_ch = up_rl & update_op_I;
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wire up_fb_ch = up_rl & update_op_II;
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wire up_con_ch = up_rl & update_op_I;
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wire up_kc_ch = up_kc & update_op_I;
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wire up_kf_ch = up_kf & update_op_I;
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wire up_pms_ch = up_pms & update_op_I;
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wire up_ams_ch = up_pms & update_op_VII;
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wire up_dt1_op = up_dt1 & update_op_II; // DT1, MUL
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wire up_mul_op = up_dt1 & update_op_VI; // DT1, MUL
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wire up_tl_op = up_tl & update_op_VII;
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wire up_ks_op = up_ks & update_op_III; // KS, AR
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wire up_amsen_op= up_amsen & update_op_VII; // AMS-EN, D1R
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wire up_dt2_op = up_dt2 & update_op_I; // DT2, D2R
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wire up_d1l_op = up_d1l & update_op_I; // D1L, RR
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wire up_ar_op = up_ks & update_op_II; // KS, AR
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wire up_d1r_op = up_amsen & update_op_II; // AMS-EN, D1R
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wire up_d2r_op = up_dt2 & update_op_II; // DT2, D2R
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wire up_rr_op = up_d1l & update_op_II; // D1L, RR
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wire [4:0] next = cur+5'd1;
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always @(posedge clk, posedge rst) begin : up_counter
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if( rst ) begin
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cur <= 5'h0;
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zero <= 1'b0;
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busy <= 1'b0;
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end
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else if(cen) begin
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cur <= next;
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zero <= next== 5'd0;
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if( &cur ) busy <= up && !busy;
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end
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end
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wire [2:0] cur_ch = cur[2:0];
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wire [3:0] keyon_op = din[6:3];
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wire [2:0] keyon_ch = din[2:0];
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jt51_kon u_kon (
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.rst (rst ),
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.clk (clk ),
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.cen (cen ),
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.keyon_op (keyon_op ),
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.keyon_ch (keyon_ch ),
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.cur_op (cur_op ),
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.cur_ch (cur_ch ),
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.up_keyon (up_keyon && busy ),
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.csm (csm ),
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.overflow_A(overflow_A),
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.keyon_II (keyon_II )
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);
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jt51_mod u_mod(
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.alg_I ( con_I ),
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.m1_enters ( m1_enters ),
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.m2_enters ( m2_enters ),
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.c1_enters ( c1_enters ),
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.c2_enters ( c2_enters ),
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.use_prevprev1 ( use_prevprev1 ),
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.use_internal_x( use_internal_x ),
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.use_internal_y( use_internal_y ),
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.use_prev2 ( use_prev2 ),
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.use_prev1 ( use_prev1 )
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);
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jt51_csr_op u_csr_op(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ), // P1
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.din ( din ),
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.up_dt1_op ( up_dt1_op ),
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.up_mul_op ( up_mul_op ),
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.up_tl_op ( up_tl_op ),
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.up_ks_op ( up_ks_op ),
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.up_amsen_op ( up_amsen_op ),
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.up_dt2_op ( up_dt2_op ),
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.up_d1l_op ( up_d1l_op ),
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.up_ar_op ( up_ar_op ),
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.up_d1r_op ( up_d1r_op ),
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.up_d2r_op ( up_d2r_op ),
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.up_rr_op ( up_rr_op ),
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.dt1 ( dt1_II ),
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.mul ( mul_VI ),
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.tl ( tl_VII ),
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.ks ( ks_III ),
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.amsen ( amsen_VII ),
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.dt2 ( dt2_I ),
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.d1l ( d1l_I ),
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.arate ( arate_II ),
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.rate1 ( rate1_II ),
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.rate2 ( rate2_II ),
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.rrate ( rrate_II )
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);
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jt51_csr_ch u_csr_ch(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ),
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.din ( din ),
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.up_rl_ch ( up_rl_ch ),
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.up_fb_ch ( up_fb_ch ),
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.up_con_ch ( up_con_ch ),
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.up_kc_ch ( up_kc_ch ),
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.up_kf_ch ( up_kf_ch ),
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.up_ams_ch ( up_ams_ch ),
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.up_pms_ch ( up_pms_ch ),
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.rl ( rl_I ),
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.fb ( fb_II ),
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.con ( con_I ),
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.kc ( kc_I ),
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.kf ( kf_I ),
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.ams ( ams_VII ),
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.pms ( pms_I )
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);
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//////////////////// Debug
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`ifndef JT51_NODEBUG
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`ifdef SIMULATION
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/* verilator lint_off PINMISSING */
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wire [4:0] cnt_aux;
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sep32_cnt u_sep32_cnt (.clk(clk), .cen(cen), .zero(zero), .cnt(cnt_aux));
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sep32 #(.width(7),.stg(1)) sep_tl(
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.clk ( clk ),
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.cen ( cen ),
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.mixed ( tl_VII ),
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.cnt ( cnt_aux )
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);
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sep32 #(.width(5),.stg(1)) sep_ar(
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.clk ( clk ),
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.cen ( cen ),
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.mixed ( arate_II ),
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.cnt ( cnt_aux )
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);
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sep32 #(.width(4),.stg(1)) sep_d1l(
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.clk ( clk ),
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.cen ( cen ),
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.mixed ( d1l_I ),
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.cnt ( cnt_aux )
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);
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sep32 #(.width(4),.stg(1)) sep_rr(
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.clk ( clk ),
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.cen ( cen ),
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.mixed ( rrate_II ),
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.cnt ( cnt_aux )
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);
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sep32 #(.width(1),.stg(1)) sep_amsen(
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.clk ( clk ),
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.cen ( cen ),
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.mixed ( amsen_VII ),
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.cnt ( cnt_aux )
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);
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/* verilator lint_on PINMISSING */
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`endif
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`endif
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endmodule
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