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60 lines
1.2 KiB
Verilog
60 lines
1.2 KiB
Verilog
// Copyright (c) 2011 MiSTer-X
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module ninjakun_input
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(
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input MCLK,
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input RESET,
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input [1:0] HWTYPE,
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input [7:0] CTR1i, // Control Panel (Negative Logic)
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input [7:0] CTR2i,
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input [7:0] CTR3i,
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input VBLK,
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input [1:0] AD0,
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input [1:0] OD0,
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input WR0,
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input [1:0] AD1,
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input [1:0] OD1,
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input WR1,
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output [7:0] INPD0,
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output [7:0] INPD1
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);
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reg [1:0] SYNCFLG;
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reg [7:0] CTR1,CTR2,CTR3;
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always @( posedge MCLK or posedge RESET ) begin
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if (RESET) begin
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SYNCFLG = 0;
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end
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else begin
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CTR1 <= CTR1i;
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CTR2 <= CTR2i;
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CTR3 <= CTR3i;
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if (WR0) begin
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if (OD0[1]) SYNCFLG[0] = 1;
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if (OD0[0]) SYNCFLG[1] = 0;
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end
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if (WR1) begin
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if (OD1[1]) SYNCFLG[0] = 0;
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if (OD1[0]) SYNCFLG[1] = 1;
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end
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end
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end
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wire [7:0] INPORT0 = CTR1;
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wire [7:0] INPORT1 = CTR2;
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wire [7:0] INPORT2 = HWTYPE[1] ? {~VBLK, CTR3[6:0]} : { 4'b0000, SYNCFLG, ~VBLK,1'b0 };
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assign INPD0 = ( AD0 == 0 ) ? INPORT0 :
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( AD0 == 1 ) ? INPORT1 :
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( AD0 == 2 ) ? INPORT2 : 8'hFF;
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assign INPD1 = ( AD1 == 0 ) ? INPORT0 :
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( AD1 == 1 ) ? INPORT1 :
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( AD1 == 2 ) ? INPORT2 : 8'hFF;
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endmodule
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