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https://github.com/Gehstock/Mist_FPGA.git
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130 lines
2.5 KiB
Systemverilog
130 lines
2.5 KiB
Systemverilog
`timescale 1ns / 1ps
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module m_range_check
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#(parameter WIDTH = 6)
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(input logic [WIDTH-1:0] val, low, high,
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output logic is_between);
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logic smallEnough, largeEnough;
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m_comparator #(WIDTH) lc(,,largeEnough, low, val);
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m_comparator #(WIDTH) hc(,,smallEnough, val, high);
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assign is_between = ~smallEnough & ~largeEnough;
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endmodule: m_range_check
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module m_offset_check
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#(parameter WIDTH = 6)
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(input logic [WIDTH-1:0] val, low, delta,
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output logic is_between);
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logic [WIDTH-1:0] high;
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m_adder #(WIDTH) add(high,, low, delta, 1'b0);
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m_range_check #(WIDTH) rc(.*);
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endmodule: m_offset_check
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module m_comparator
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#(parameter WIDTH = 6)
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(output logic AltB, AeqB, AgtB,
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input logic [WIDTH-1:0] A, B);
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assign AltB = (A < B);
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assign AeqB = (A == B);
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assign AgtB = (A > B);
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endmodule: m_comparator
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module m_adder
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#(parameter WIDTH = 6)
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(output logic [WIDTH-1:0] Sum,
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output logic Cout,
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input logic [WIDTH-1:0] A, B,
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input logic Cin);
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assign {Cout, Sum} = A + B + Cin;
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endmodule: m_adder
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module m_mux
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#(parameter WIDTH = 6)
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(output logic Y,
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input logic [WIDTH-1:0] I,
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input logic [$clog2(WIDTH)-1:0] Sel);
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assign Y = I[Sel];
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endmodule: m_mux
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module m_mux2to1
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#(parameter WIDTH = 6)
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(output logic [WIDTH-1:0] Y,
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input logic [WIDTH-1:0] I0, I1,
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input logic Sel);
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assign Y = (Sel ? I1 : I0);
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endmodule: m_mux2to1
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module m_decoder
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#(parameter WIDTH = 6)
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(output logic [(1 << WIDTH)-1:0] D,
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input logic [WIDTH-1:0] I,
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input logic en);
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assign D = en << I;
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endmodule: m_decoder
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module m_register
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#(parameter WIDTH = 6)
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(output logic [WIDTH-1:0] Q,
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input logic [WIDTH-1:0] D,
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input logic clr, en, clk);
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always_ff @(posedge clk)
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if(clr)
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Q <= 0;
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else if(en)
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Q <= D;
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endmodule: m_register
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module m_counter
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#(parameter WIDTH = 6)
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(output logic [WIDTH-1:0] Q,
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input logic [WIDTH-1:0] D,
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input logic clk, clr, load, en, up);
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always_ff @(posedge clk) begin
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if(clr)
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Q <= 0;
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else if(load)
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Q <= D;
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else if(en)
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Q <= (up ? Q + 1 : Q - 1);
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end
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endmodule: m_counter
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module m_shift_register
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#(parameter WIDTH = 6)
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(output logic [WIDTH-1:0] Q,
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input logic clk, en, left, s_in, clr);
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always_ff @(posedge clk)
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if (clr) begin
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Q <= 'd0;
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end
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else if(en) begin
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if(left) begin
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Q <= (Q << 1);
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Q[0] <= s_in;
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end
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else begin
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Q <= (Q >> 1);
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Q[WIDTH-1] <= s_in;
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end
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end
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endmodule: m_shift_register
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