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66 lines
3.5 KiB
Verilog
66 lines
3.5 KiB
Verilog
/*******************************************************************************************/
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/** **/
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/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
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/** **/
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/** alu shifter module Rev 0.0 06/13/2012 **/
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/** **/
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/*******************************************************************************************/
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module alu_shft (shft_c, shft_out, alub_in, aluop_reg, carry_bit);
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input carry_bit; /* carry flag input */
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input [7:0] alub_in; /* alu b input */
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input [`AOP_IDX:0] aluop_reg; /* alu operation control subset */
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output shft_c; /* alu shifter carry output */
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output [7:0] shft_out; /* alu shifter output */
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/*****************************************************************************************/
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/* */
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/* signal declarations */
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/* */
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/*****************************************************************************************/
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reg shft_c; /* shifter carry output */
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reg [7:0] shft_out; /* shifter output */
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/*****************************************************************************************/
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/* */
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/* alu shifter function */
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/* */
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/*****************************************************************************************/
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always @ (aluop_reg or alub_in) begin
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casex (aluop_reg) //synopsys parallel_case
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`AOP_RL,
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`AOP_RLA: shft_c = alub_in[7];
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`AOP_RLC,
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`AOP_RLCA: shft_c = alub_in[7];
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`AOP_RR,
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`AOP_RRA: shft_c = alub_in[0];
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`AOP_RRC,
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`AOP_RRCA: shft_c = alub_in[0];
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`AOP_SLL,
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`AOP_SLA: shft_c = alub_in[7];
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`AOP_SRA: shft_c = alub_in[0];
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`AOP_SRL: shft_c = alub_in[0];
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default: shft_c = 1'b0;
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endcase
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end
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always @ (aluop_reg or alub_in or carry_bit) begin
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casex (aluop_reg) //synopsys parallel_case
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`AOP_RL,
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`AOP_RLA: shft_out = {alub_in[6:0], carry_bit};
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`AOP_RLC,
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`AOP_RLCA: shft_out = {alub_in[6:0], alub_in[7]};
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`AOP_RR,
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`AOP_RRA: shft_out = {carry_bit, alub_in[7:1]};
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`AOP_RRC,
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`AOP_RRCA: shft_out = {alub_in[0], alub_in[7:1]};
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`AOP_SLA: shft_out = {alub_in[6:0], 1'b0};
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`AOP_SLL: shft_out = {alub_in[6:0], 1'b1};
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`AOP_SRA: shft_out = {alub_in[7], alub_in[7:1]};
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`AOP_SRL: shft_out = {1'b0, alub_in[7:1]};
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default: shft_out = 8'h00;
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endcase
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end
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endmodule |