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50 lines
1.5 KiB
VHDL
50 lines
1.5 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- $Id: alu_pack-p.vhd,v 1.2 2004/04/04 14:18:53 arniml Exp $
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.t48_pack.word_width_c;
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package alu_pack is
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-----------------------------------------------------------------------------
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-- The ALU operations
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-----------------------------------------------------------------------------
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type alu_op_t is (ALU_AND, ALU_OR, ALU_XOR,
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ALU_CPL, ALU_CLR,
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ALU_RL, ALU_RR,
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ALU_SWAP,
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ALU_DEC, ALU_INC,
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ALU_ADD,
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ALU_CONCAT,
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ALU_NOP);
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-----------------------------------------------------------------------------
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-- The dedicated ALU arithmetic types.
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-----------------------------------------------------------------------------
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subtype alu_operand_t is std_logic_vector(word_width_c downto 0);
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end alu_pack;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: alu_pack-p.vhd,v $
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-- Revision 1.2 2004/04/04 14:18:53 arniml
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-- add measures to implement XCHD
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--
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- initial check-in
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--
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--
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-------------------------------------------------------------------------------
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