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59 lines
1.7 KiB
Verilog
59 lines
1.7 KiB
Verilog
module pla_6703(
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input [15:10]A,
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input [3:0]DI,
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output [11:8]DO,
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input CLK,//CLK
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input BA,//BA
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input RW_IN,// RW
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output reg RAM,//RAM invert
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output reg EXRAM,//EXRAM invert
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output reg VIC,//VIC invert
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output reg SID,//SID invert
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output reg CIA,//CIA_PLA invert
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output reg COLRAM,//COLRAM invert
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output reg ROML,//ROML invert
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output reg ROMH,//ROMH invert
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output reg BUF,//to the 4066 COLOR Ram DATA
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output reg RW_OUT//RW_PLA invert
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);
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always @ (posedge CLK)
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begin
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RAM = ~(~A[11] & ~A[12] & ~A[13] & ~A[14] & ~A[15] & CLK & BA);
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EXRAM = ~(A[11] & ~A[12] & ~A[13] & ~A[14] & ~A[15] & CLK & BA);
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ROML = ~(~A[13] & ~A[14] & A[15] & CLK & BA);
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ROMH = ~(A[13] & A[14] & A[15] & CLK & BA);
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SID = ~(A[10] & ~A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
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VIC = ~(~A[10] & ~A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
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COLRAM = ~(~A[10] & A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
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BUF = (~A[10] & A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
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CIA = ~(A[10] & A[11] & A[12] & ~A[13] & A[14] & A[15] & CLK & BA);
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RW_OUT = ~(CLK & ~RW_IN);
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end
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//GAL Code
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/*!
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RAM = !A11 & !A12 & !A13 & !A14 & !A15 & CLK & BA
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!EXRAM = A11 & !A12 & !A13 & !A14 & !A15 & CLK & BA
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# A11 & !A12 & !A13 & !CLK
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# A11 & !A12 & !A13 & !BA;
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!ROML = !A13 & !A14 & A15 & CLK & BA;
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!ROMH = A13 & A14 & A15 & CLK & BA
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# A12 & A13 & !CLK
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# A12 & A13 & !BA;
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!SID = A10 & !A11 & A12 & !A13 & A14 & A15 & CLK & BA;
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!VIC = !A10 & !A11 & A12 & !A13 & A14 & A15 & CLK & BA;
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!COLRAM = !A10 & A11 & A12 & !A13 & A14 & A15 & CLK & BA
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# !CLK
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# !BA;
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BUF = !A10 & A11 & A12 & !A13 & A14 & A15 & CLK & BA;
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!CIA = A10 & A11 & A12 & !A13 & A14 & A15 & CLK & BA;
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!RW_OUT = CLK & !RW_IN;*/
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endmodule
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