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43 lines
867 B
Verilog
43 lines
867 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 18:04:18 02/22/2008
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// Design Name:
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// Module Name: mram
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module mram(addr,din,dout,en,we);
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input [14:0] addr;
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input [7:0] din;
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output [7:0] dout;
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input en, we;
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reg [7:0] mem [0:32767];
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wire WRITE, READ;
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always @( WRITE or din ) begin
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if ( WRITE )
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mem[ addr ] <= din;
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end
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assign READ = ~we & en;
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assign WRITE = we & en;
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assign dout = READ ? mem[ addr ] : 8'hzz;
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initial $readmemh( "roms/mon_rom_jp.hex.hex", mem );
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endmodule
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