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50 lines
890 B
Verilog
50 lines
890 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 08:54:34 02/19/2008
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// Design Name:
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// Module Name: clock_gen
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module sound(CLK_50MHZ, SW, TP1);
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input CLK_50MHZ;
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input SW;
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output TP1;
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reg [14:0] count = 0;
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reg [14:0] count2 = 1;
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reg CLK = 0;
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wire TP1;
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always @(posedge CLK_50MHZ)
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begin
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count <= count + 1;
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end
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always @(posedge count[12])
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begin
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if ( count2 >= SW )
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begin
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CLK <= SW != 0 ? ~CLK: CLK;
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count2 <= 1;
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end else
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begin
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count2 <= count2 + 1;
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end
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end
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assign TP1 = CLK;
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endmodule
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