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63 lines
1.7 KiB
Verilog
63 lines
1.7 KiB
Verilog
/* This file is part of JT89.
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JT89 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT89 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT89. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: December, 1st 2018
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This work was originally based in the implementation found on the
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SMS core of MiST
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*/
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module jt89_vol(
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input clk,
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input clk_en,
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input rst,
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input din,
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input [3:0] vol,
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output reg signed [8:0] snd
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);
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reg [7:0] max;
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always @(*)
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case ( vol ) // 2dB per LSB (20*log10)
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4'd0: max = 8'd255;
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4'd1: max = 8'd203;
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4'd2: max = 8'd161;
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4'd3: max = 8'd128;
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4'd4: max = 8'd102;
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4'd5: max = 8'd81;
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4'd6: max = 8'd64;
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4'd7: max = 8'd51;
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4'd8: max = 8'd40;
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4'd9: max = 8'd32;
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4'd10: max = 8'd26;
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4'd11: max = 8'd20;
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4'd12: max = 8'd16;
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4'd13: max = 8'd13;
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4'd14: max = 8'd10;
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4'd15: max = 8'd0;
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endcase
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always @(posedge clk)
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if( rst )
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snd <= 9'd0;
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else if( clk_en )
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snd <= din ? {1'b0,max} : -{1'b0,max};
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endmodule |