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https://github.com/Gehstock/Mist_FPGA.git
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359 lines
9.8 KiB
Verilog
359 lines
9.8 KiB
Verilog
/* This file is part of JT51.
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JT51 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT51 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT51. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-10-2016
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*/
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`timescale 1ns / 1ps
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module jt51(
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input rst, // reset
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input clk, // main clock
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input cen, // clock enable
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input cen_p1, // clock enable at half the speed
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input cs_n, // chip select
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input wr_n, // write
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input a0,
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input [7:0] din, // data in
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output [7:0] dout, // data out
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// peripheral control
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output ct1,
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output ct2,
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output irq_n, // I do not synchronize this signal
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// Low resolution output (same as real chip)
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output sample, // marks new output sample
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output signed [15:0] left,
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output signed [15:0] right,
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// Full resolution output
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output signed [15:0] xleft,
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output signed [15:0] xright,
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// unsigned outputs for sigma delta converters, full resolution
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output [15:0] dacleft,
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output [15:0] dacright
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);
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assign dacleft = { ~xleft [15], xleft[14:0] };
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assign dacright = { ~xright[15], xright[14:0] };
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// Timers
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wire [9:0] value_A;
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wire [7:0] value_B;
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wire load_A, load_B;
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wire enable_irq_A, enable_irq_B;
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wire clr_flag_A, clr_flag_B;
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wire flag_A, flag_B, overflow_A;
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wire zero;
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jt51_timers u_timers(
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.clk ( clk ),
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.cen ( cen_p1 ),
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.rst ( rst ),
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.zero ( zero ),
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.value_A ( value_A ),
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.value_B ( value_B ),
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.load_A ( load_A ),
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.load_B ( load_B ),
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.enable_irq_A( enable_irq_A ),
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.enable_irq_B( enable_irq_B ),
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.clr_flag_A ( clr_flag_A ),
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.clr_flag_B ( clr_flag_B ),
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.flag_A ( flag_A ),
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.flag_B ( flag_B ),
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.overflow_A ( overflow_A ),
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.irq_n ( irq_n )
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);
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/*verilator tracing_off*/
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`ifndef JT51_ONLYTIMERS
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`define YM_TIMER_CTRL 8'h14
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wire [1:0] rl_I;
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wire [2:0] fb_II;
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wire [2:0] con_I;
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wire [6:0] kc_I;
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wire [5:0] kf_I;
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wire [2:0] pms_I;
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wire [1:0] ams_VII;
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wire [2:0] dt1_II;
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wire [3:0] mul_VI;
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wire [6:0] tl_VII;
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wire [1:0] ks_III;
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wire [4:0] arate_II;
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wire amsen_VII;
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wire [4:0] rate1_II;
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wire [1:0] dt2_I;
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wire [4:0] rate2_II;
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wire [3:0] d1l_I;
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wire [3:0] rrate_II;
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wire [1:0] cur_op;
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assign sample =zero;
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wire keyon_II;
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wire [7:0] lfo_freq;
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wire [1:0] lfo_w;
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wire lfo_rst;
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wire [6:0] am;
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wire [7:0] pm;
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wire [6:0] amd, pmd;
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wire m1_enters, m2_enters, c1_enters, c2_enters;
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wire use_prevprev1,use_internal_x,use_internal_y, use_prev2,use_prev1;
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jt51_lfo u_lfo(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen ), // should it be cen_p1?
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.zero ( zero ),
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.lfo_rst ( lfo_rst ),
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.lfo_freq ( lfo_freq ),
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.lfo_w ( lfo_w ),
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.lfo_amd ( amd ),
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.lfo_pmd ( pmd ),
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.am ( am ),
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.pm_u ( pm )
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);
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wire [ 4:0] keycode_III;
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wire [ 9:0] ph_X;
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wire pg_rst_III;
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jt51_pg u_pg(
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.rst ( rst ),
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.clk ( clk ), // P1
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.cen ( cen_p1 ),
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.zero ( zero ),
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// Channel frequency
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.kc_I ( kc_I ),
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.kf_I ( kf_I ),
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// Operator multiplying
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.mul_VI ( mul_VI ),
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// Operator detuning
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.dt1_II ( dt1_II ),
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.dt2_I ( dt2_I ),
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// phase modulation from LFO
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.pms_I ( pms_I ),
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.pm ( pm ),
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// phase operation
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.pg_rst_III ( pg_rst_III ),
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.keycode_III( keycode_III ),
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.pg_phase_X ( ph_X )
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);
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`ifdef TEST_SUPPORT
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wire test_eg, test_op0;
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`endif
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wire [9:0] eg_XI;
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jt51_eg u_eg(
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`ifdef TEST_SUPPORT
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.test_eg ( test_eg ),
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`endif
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen_p1 ),
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.zero ( zero ),
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// envelope configuration
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.keycode_III(keycode_III), // used in stage III
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.arate_II ( arate_II ),
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.rate1_II ( rate1_II ),
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.rate2_II ( rate2_II ),
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.rrate_II ( rrate_II ),
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.d1l_I ( d1l_I ),
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.ks_III ( ks_III ),
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// envelope operation
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.keyon_II ( keyon_II ),
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.pg_rst_III ( pg_rst_III),
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// envelope number
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.tl_VII ( tl_VII ),
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.am ( am ),
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.ams_VII ( ams_VII ),
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.amsen_VII ( amsen_VII ),
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.eg_XI ( eg_XI )
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);
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wire signed [13:0] op_out;
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jt51_op u_op(
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`ifdef TEST_SUPPORT
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.test_eg ( test_eg ),
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.test_op0 ( test_op0 ),
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`endif
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen_p1 ),
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.pg_phase_X ( ph_X ),
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.con_I ( con_I ),
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.fb_II ( fb_II ),
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// volume
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.eg_atten_XI ( eg_XI ),
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// modulation
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.m1_enters ( m1_enters ),
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.c1_enters ( c1_enters ),
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// Operator
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.use_prevprev1 ( use_prevprev1 ),
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.use_internal_x ( use_internal_x ),
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.use_internal_y ( use_internal_y ),
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.use_prev2 ( use_prev2 ),
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.use_prev1 ( use_prev1 ),
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.test_214 ( 1'b0 ),
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`ifdef SIMULATION
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.zero ( zero ),
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`endif
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// output data
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.op_XVII ( op_out )
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);
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wire [4:0] nfrq;
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wire [10:0] noise_out;
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wire ne, op31_acc, op31_no;
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jt51_noise u_noise(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen_p1 ),
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.nfrq ( nfrq ),
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.eg ( eg_XI ),
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.out ( noise_out ),
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.op31_no( op31_no )
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);
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jt51_acc u_acc(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen_p1 ),
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.m1_enters ( m1_enters ),
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.m2_enters ( m2_enters ),
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.c1_enters ( c1_enters ),
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.c2_enters ( c2_enters ),
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.op31_acc ( op31_acc ),
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.rl_I ( rl_I ),
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.con_I ( con_I ),
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.op_out ( op_out ),
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.ne ( ne ),
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.noise ( noise_out ),
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.left ( left ),
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.right ( right ),
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.xleft ( xleft ),
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.xright ( xright )
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);
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`else
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assign left = 16'd0;
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assign right = 16'd0;
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assign xleft = 16'd0;
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assign xright = 16'd0;
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`endif
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wire busy;
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wire write = !cs_n && !wr_n;
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assign dout = { busy, 5'h0, flag_B, flag_A };
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/*verilator tracing_on*/
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jt51_mmr u_mmr(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( cen_p1 ),
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.a0 ( a0 ),
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.write ( write ),
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.din ( din ),
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.busy ( busy ),
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// CT
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.ct1 ( ct1 ),
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.ct2 ( ct2 ),
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// LFO
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.lfo_freq ( lfo_freq ),
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.lfo_w ( lfo_w ),
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.lfo_amd ( amd ),
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.lfo_pmd ( pmd ),
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.lfo_rst ( lfo_rst ),
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// Noise
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.ne ( ne ),
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.nfrq ( nfrq ),
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// Timers
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.value_A ( value_A ),
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.value_B ( value_B ),
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.load_A ( load_A ),
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.load_B ( load_B ),
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.enable_irq_A( enable_irq_A ),
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.enable_irq_B( enable_irq_B ),
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.clr_flag_A ( clr_flag_A ),
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.clr_flag_B ( clr_flag_B ),
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.overflow_A ( overflow_A ),
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`ifdef TEST_SUPPORT
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// Test
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.test_eg ( test_eg ),
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.test_op0 ( test_op0 ),
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`endif
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// REG
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.rl_I ( rl_I ),
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.fb_II ( fb_II ),
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.con_I ( con_I ),
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.kc_I ( kc_I ),
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.kf_I ( kf_I ),
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.pms_I ( pms_I ),
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.ams_VII ( ams_VII ),
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.dt1_II ( dt1_II ),
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.mul_VI ( mul_VI ),
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.tl_VII ( tl_VII ),
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.ks_III ( ks_III ),
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.arate_II ( arate_II ),
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.amsen_VII ( amsen_VII ),
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.rate1_II ( rate1_II ),
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.dt2_I ( dt2_I ),
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.rate2_II ( rate2_II ),
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.d1l_I ( d1l_I ),
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.rrate_II ( rrate_II ),
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.keyon_II ( keyon_II ),
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.cur_op ( cur_op ),
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.op31_no ( op31_no ),
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.op31_acc ( op31_acc ),
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.zero ( zero ),
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.m1_enters ( m1_enters ),
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.m2_enters ( m2_enters ),
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.c1_enters ( c1_enters ),
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.c2_enters ( c2_enters ),
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// Operator
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.use_prevprev1 ( use_prevprev1 ),
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.use_internal_x ( use_internal_x ),
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.use_internal_y ( use_internal_y ),
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.use_prev2 ( use_prev2 ),
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.use_prev1 ( use_prev1 )
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);
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`ifdef SIMULATION
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`ifndef VERILATOR
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integer fsnd;
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initial begin
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fsnd=$fopen("jt51.raw","wb");
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end
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always @(posedge zero) begin
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$fwrite(fsnd,"%u", {xleft, xright});
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end
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`endif
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`endif
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endmodule
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