1
0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-04-30 13:52:10 +00:00
Files
Gehstock.Mist_FPGA/common/CPU/t48/p2-c.vhd
2020-05-13 15:54:31 +02:00

18 lines
387 B
VHDL

-------------------------------------------------------------------------------
--
-- The Port 2 unit.
-- Implements the Port 2 logic.
--
-- $Id: p2-c.vhd,v 1.2 2005/06/11 10:08:43 arniml Exp $
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t48_p2_rtl_c0 of t48_p2 is
for rtl
end for;
end t48_p2_rtl_c0;