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https://github.com/Gehstock/Mist_FPGA.git
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90 lines
1.4 KiB
Verilog
90 lines
1.4 KiB
Verilog
`timescale 1ns / 1ps
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module mc6809
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(
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input CLK,
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input CLKEN,
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input nRESET,
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input CPU,
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output reg E,
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output reg riseE,
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output reg fallE, // everything except interrupts/dma registered/latched here
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output reg Q,
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output reg riseQ,
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output reg fallQ, // NMI,IRQ,FIRQ,DMA,HALT registered here
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input [7:0] Din,
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output [7:0] Dout,
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output [15:0] ADDR,
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output RnW,
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input nIRQ,
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input nFIRQ,
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input nNMI,
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input nHALT
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);
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cpu09 cpu1
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(
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.clk(CLK),
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.ce(fallE),
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.rst(~nRESET | CPU),
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.addr(ADDR1),
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.rw(RnW1),
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.data_out(Dout1),
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.data_in(Din),
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.irq(~nIRQ),
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.firq(~nFIRQ),
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.nmi(~nNMI),
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.halt(~nHALT)
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);
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mc6809is cpu2
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(
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.CLK(CLK),
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.D(Din),
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.DOut(Dout2),
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.ADDR(ADDR2),
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.RnW(RnW2),
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.fallE_en(fallE),
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.fallQ_en(fallQ),
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.nIRQ(nIRQ),
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.nFIRQ(nFIRQ),
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.nNMI(nNMI),
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.nHALT(nHALT),
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.nRESET(nRESET & CPU),
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.nDMABREQ(1)
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);
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wire [7:0] Dout1,Dout2;
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wire [15:0] ADDR1,ADDR2;
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wire RnW1,RnW2;
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assign Dout = CPU ? Dout2 : Dout1;
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assign ADDR = CPU ? ADDR2 : ADDR1;
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assign RnW = CPU ? RnW2 : RnW1;
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always @(posedge CLK)
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begin
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reg [1:0] clk_phase =0;
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fallE <= 0;
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fallQ <= 0;
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riseE <= 0;
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riseQ <= 0;
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if (CLKEN) begin
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clk_phase <= clk_phase + 1'd1;
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case (clk_phase)
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2'b00: begin E <= 0; fallE <= 1; end
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2'b01: begin Q <= 1; riseQ <= 1; end
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2'b10: begin E <= 1; riseE <= 1; end
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2'b11: begin Q <= 0; fallQ <= 1; end
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endcase
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end
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end
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endmodule
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