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95 lines
4.8 KiB
VHDL
95 lines
4.8 KiB
VHDL
-------------------------------------------------------------------------------
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-- --
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-- X X XXXXXX XXXXXX XXXXXX XXXXXX X --
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-- XX XX X X X X X X X XX --
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-- X X X X X X X X X X X X --
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-- X X X X X X X X X X X X --
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-- X X X X XXXXXX X X XXXXXX X --
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-- X X X X X X X X X --
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-- X X X X X X X X X --
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-- X X X X X X X X X X --
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-- X X XXXXXX XXXXXX XXXXXX XXXXXX X --
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-- --
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-- --
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-- O R E G A N O S Y S T E M S --
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-- --
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-- Design & Consulting --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- Web: http://www.oregano.at/ --
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-- --
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-- Contact: mc8051@oregano.at --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- MC8051 - VHDL 8051 Microcontroller IP Core --
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-- Copyright (C) 2001 OREGANO SYSTEMS --
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file LGPL.TXT. --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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--
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--
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-- Author: Roland Höller
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--
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-- Filename: addsub_cy_rtl.vhd
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--
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-- Date of Creation: Mon Aug 9 12:14:48 1999
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--
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-- Version: $Revision: 1.4 $
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--
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-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $
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--
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--
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-- Description: Adder/Subtractor with carry/borrow and arbitrary
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-- data width.
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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architecture rtl of addsub_cy is
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begin
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-- purpose: Simple adder/subtractor with carry/borrow
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-- type : combinational
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-- inputs : opa_i, opb_i, addsub_i
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-- outputs: cy_o, rslt_o
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p_addsub: process (opa_i, opb_i, addsub_i, cy_i)
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variable v_a : unsigned(DWIDTH downto 0);
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variable v_b : unsigned(DWIDTH downto 0);
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variable v_result : std_logic_vector(DWIDTH+1 downto 0);
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begin -- process p_addsub
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v_a(DWIDTH downto 1) := unsigned(opa_i);
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v_b(DWIDTH downto 1) := unsigned(opb_i);
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if addsub_i = '1' then
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v_a(0) := '1';
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v_b(0) := cy_i;
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v_result := conv_unsigned(v_a,DWIDTH+2) + v_b;
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else
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v_a(0) := '0';
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v_b(0) := cy_i;
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v_result := conv_unsigned(v_a,DWIDTH+2) - v_b;
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end if;
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cy_o <= v_result(DWIDTH+1);
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rslt_o <= v_result(DWIDTH downto 1);
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end process p_addsub;
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end rtl;
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