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433 lines
18 KiB
VHDL
433 lines
18 KiB
VHDL
-------------------------------------------------------------------------------
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-- --
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-- X X XXXXXX XXXXXX XXXXXX XXXXXX X --
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-- XX XX X X X X X X X XX --
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-- X X X X X X X X X X X X --
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-- X X X X X X X X X X X X --
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-- X X X X XXXXXX X X XXXXXX X --
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-- X X X X X X X X X --
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-- X X X X X X X X X --
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-- X X X X X X X X X X --
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-- X X XXXXXX XXXXXX XXXXXX XXXXXX X --
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-- --
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-- --
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-- O R E G A N O S Y S T E M S --
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-- --
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-- Design & Consulting --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- Web: http://www.oregano.at/ --
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-- --
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-- Contact: mc8051@oregano.at --
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-- --
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-------------------------------------------------------------------------------
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-- --
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-- MC8051 - VHDL 8051 Microcontroller IP Core --
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-- Copyright (C) 2001 OREGANO SYSTEMS --
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-- --
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-- This library is free software; you can redistribute it and/or --
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-- modify it under the terms of the GNU Lesser General Public --
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-- License as published by the Free Software Foundation; either --
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-- version 2.1 of the License, or (at your option) any later version. --
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-- --
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-- This library is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
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-- Lesser General Public License for more details. --
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-- --
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-- Full details of the license can be found in the file LGPL.TXT. --
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-- --
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-- You should have received a copy of the GNU Lesser General Public --
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-- License along with this library; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-------------------------------------------------------------------------------
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--
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--
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-- Author: Roland Höller
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--
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-- Filename: alumux_rtl.vhd
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--
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-- Date of Creation: Mon Aug 9 12:14:48 1999
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--
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-- Version: $Revision: 1.6 $
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--
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-- Date of Latest Version: $Date: 2002-01-07 12:17:44 $
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--
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--
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-- Description: Select data path according to the actual command.
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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architecture rtl of alumux is
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constant DA : std_logic_vector(5 downto 0) := "100000";
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constant ADD_ACC_RAM : std_logic_vector(5 downto 0) := "100001";
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constant ADD_ACC_ROM : std_logic_vector(5 downto 0) := "100010";
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constant ADDC_ACC_RAM : std_logic_vector(5 downto 0) := "100011";
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constant ADDC_ACC_ROM : std_logic_vector(5 downto 0) := "100100";
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constant AND_ACC_RAM : std_logic_vector(5 downto 0) := "100101";
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constant AND_ACC_ROM : std_logic_vector(5 downto 0) := "100110";
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constant AND_RAM_ROM : std_logic_vector(5 downto 0) := "100111";
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constant SUB_ACC_RAM : std_logic_vector(5 downto 0) := "101000";
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constant SUB_ACC_ROM : std_logic_vector(5 downto 0) := "101001";
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constant MUL_ACC_RAM : std_logic_vector(5 downto 0) := "101010";
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constant DIV_ACC_RAM : std_logic_vector(5 downto 0) := "101011";
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constant OR_RAM_ACC : std_logic_vector(5 downto 0) := "101100";
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constant OR_ROM_ACC : std_logic_vector(5 downto 0) := "101101";
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constant OR_ROM_RAM : std_logic_vector(5 downto 0) := "101110";
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constant XOR_RAM_ACC : std_logic_vector(5 downto 0) := "101111";
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constant XOR_ROM_ACC : std_logic_vector(5 downto 0) := "110000";
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constant XOR_ROM_RAM : std_logic_vector(5 downto 0) := "110001";
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constant RL_ACC : std_logic_vector(5 downto 0) := "110010";
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constant RLC_ACC : std_logic_vector(5 downto 0) := "110011";
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constant RR_ACC : std_logic_vector(5 downto 0) := "110100";
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constant RRC_ACC : std_logic_vector(5 downto 0) := "110101";
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constant INV_ACC : std_logic_vector(5 downto 0) := "110110";
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constant INV_RAM : std_logic_vector(5 downto 0) := "110111";
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constant DEC_ACC : std_logic_vector(5 downto 0) := "111000";
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constant DEC_RAM : std_logic_vector(5 downto 0) := "111001";
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constant COMP_RAM_ACC : std_logic_vector(5 downto 0) := "111010";
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constant COMP_ROM_ACC : std_logic_vector(5 downto 0) := "111011";
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constant COMP_ROM_RAM : std_logic_vector(5 downto 0) := "111100";
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constant INC_ACC : std_logic_vector(5 downto 0) := "111110";
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constant INC_RAM : std_logic_vector(5 downto 0) := "111111";
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constant NOP : std_logic_vector(3 downto 0) := "0000";
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constant LAND : std_logic_vector(3 downto 0) := "0011";
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constant LOR : std_logic_vector(3 downto 0) := "0101";
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constant LXOR : std_logic_vector(3 downto 0) := "0110";
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constant RL : std_logic_vector(3 downto 0) := "0111";
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constant RLC : std_logic_vector(3 downto 0) := "1000";
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constant RR : std_logic_vector(3 downto 0) := "1001";
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constant RRC : std_logic_vector(3 downto 0) := "1010";
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constant COMP : std_logic_vector(3 downto 0) := "1011";
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constant INV : std_logic_vector(3 downto 0) := "1100";
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begin
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-- Multiplex the input data and generate the command for the alu core.
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p_alucore_mux : process (rom_data_i,
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ram_data_i,
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acc_i,
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cmd_i)
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begin
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case cmd_i is
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when AND_ACC_RAM =>
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alu_cmd_o <= LAND;
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op_a_o <= acc_i;
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op_b_o <= ram_data_i;
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when AND_ACC_ROM =>
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alu_cmd_o <= LAND;
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op_a_o <= acc_i;
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op_b_o <= rom_data_i;
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when AND_RAM_ROM =>
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alu_cmd_o <= LAND;
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op_a_o <= ram_data_i;
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op_b_o <= rom_data_i;
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when OR_RAM_ACC =>
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alu_cmd_o <= LOR;
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op_a_o <= acc_i;
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op_b_o <= ram_data_i;
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when OR_ROM_ACC =>
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alu_cmd_o <= LOR;
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op_a_o <= acc_i;
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op_b_o <= rom_data_i;
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when OR_ROM_RAM =>
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alu_cmd_o <= LOR;
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op_a_o <= rom_data_i;
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op_b_o <= ram_data_i;
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when XOR_RAM_ACC =>
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alu_cmd_o <= LXOR;
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op_a_o <= acc_i;
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op_b_o <= ram_data_i;
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when XOR_ROM_ACC =>
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alu_cmd_o <= LXOR;
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op_a_o <= acc_i;
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op_b_o <= rom_data_i;
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when XOR_ROM_RAM =>
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alu_cmd_o <= LXOR;
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op_a_o <= rom_data_i;
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op_b_o <= ram_data_i;
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when RL_ACC =>
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alu_cmd_o <= RL;
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op_a_o <= acc_i;
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op_b_o <= ( others => '0' );
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when RLC_ACC =>
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alu_cmd_o <= RLC;
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op_a_o <= acc_i;
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op_b_o <= ( others => '0' );
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when RR_ACC =>
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alu_cmd_o <= RR;
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op_a_o <= acc_i;
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op_b_o <= ( others => '0' );
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when RRC_ACC =>
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alu_cmd_o <= RRC;
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op_a_o <= acc_i;
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op_b_o <= ( others => '0' );
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when INV_ACC =>
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alu_cmd_o <= INV;
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op_a_o <= acc_i;
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op_b_o <= ( others => '0' );
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when INV_RAM =>
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alu_cmd_o <= INV;
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op_a_o <= ram_data_i;
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op_b_o <= ( others => '0' );
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when COMP_RAM_ACC =>
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alu_cmd_o <= COMP;
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op_a_o <= acc_i;
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op_b_o <= ram_data_i;
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when COMP_ROM_ACC =>
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alu_cmd_o <= COMP;
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op_a_o <= acc_i;
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op_b_o <= rom_data_i;
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when COMP_ROM_RAM =>
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alu_cmd_o <= COMP;
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op_a_o <= ram_data_i;
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op_b_o <= rom_data_i;
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when others =>
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alu_cmd_o <= NOP;
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op_a_o <= ( others => '0' );
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op_b_o <= ( others => '0' );
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end case;
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end process p_alucore_mux;
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-- Multiplex the input data for all the functions not included in the
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-- alu core.
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p_ext_mux : process (ram_data_i,
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rom_data_i,
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acc_i,
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cy_i,
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cmd_i)
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begin
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case cmd_i is
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when DA =>
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dcml_data_o <= acc_i;
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '0';
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addsub_cy_o <= '0';
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opa_o <= ( others => '0' );
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opb_o <= ( others => '0' );
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when DIV_ACC_RAM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= acc_i;
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dvsor_o <= ram_data_i;
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addsub_o <= '0';
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addsub_cy_o <= '0';
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opa_o <= ( others => '0' );
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opb_o <= ( others => '0' );
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when MUL_ACC_RAM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= acc_i;
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mltplctr_o <= ram_data_i;
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '0';
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addsub_cy_o <= '0';
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opa_o <= ( others => '0' );
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opb_o <= ( others => '0' );
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when INC_ACC =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '1';
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addsub_cy_o <= '0';
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opa_o <= acc_i;
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opb_o <= std_logic_vector(conv_unsigned(1, DWIDTH));
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when INC_RAM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '1';
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addsub_cy_o <= '0';
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opa_o <= ram_data_i;
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opb_o <= std_logic_vector(conv_unsigned(1, DWIDTH));
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when DEC_ACC =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '0';
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addsub_cy_o <= '0';
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opa_o <= acc_i;
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opb_o <= std_logic_vector(conv_unsigned(1, DWIDTH));
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when DEC_RAM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '0';
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addsub_cy_o <= '0';
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opa_o <= ram_data_i;
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opb_o <= std_logic_vector(conv_unsigned(1, DWIDTH));
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when SUB_ACC_RAM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '0';
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addsub_cy_o <= cy_i((DWIDTH-1)/4);
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opa_o <= acc_i;
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opb_o <= ram_data_i;
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when SUB_ACC_ROM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '0';
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addsub_cy_o <= cy_i((DWIDTH-1)/4);
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opa_o <= acc_i;
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opb_o <= rom_data_i;
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when ADD_ACC_RAM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '1';
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addsub_cy_o <= '0';
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opa_o <= acc_i;
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opb_o <= ram_data_i;
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when ADD_ACC_ROM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '1';
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addsub_cy_o <= '0';
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opa_o <= acc_i;
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opb_o <= rom_data_i;
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when ADDC_ACC_RAM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '1';
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addsub_cy_o <= cy_i((DWIDTH-1)/4);
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opa_o <= acc_i;
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opb_o <= ram_data_i;
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when ADDC_ACC_ROM =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '1';
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addsub_cy_o <= cy_i((DWIDTH-1)/4);
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opa_o <= acc_i;
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opb_o <= rom_data_i;
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when others =>
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dcml_data_o <= ( others => '0' );
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mltplcnd_o <= ( others => '0' );
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mltplctr_o <= ( others => '0' );
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dvdnd_o <= ( others => '0' );
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dvsor_o <= ( others => '0' );
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addsub_o <= '0';
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addsub_cy_o <= '0';
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opa_o <= ( others => '0' );
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opb_o <= ( others => '0' );
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end case;
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end process p_ext_mux;
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-- Multiplex the results for all the units contributing to the ALU.
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p_rslt_mux : process (ram_data_i,
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cy_i,
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ov_i,
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product_i,
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qutnt_i,
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rmndr_i,
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result_i,
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new_cy_i,
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addsub_rslt_i,
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addsub_cy_i,
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addsub_ov_i,
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dcml_data_i,
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dcml_cy_i,
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cmd_i)
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begin
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case cmd_i is
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when DA =>
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if (C_IMPL_DA /= 0) then
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result_a_o <= dcml_data_i;
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result_b_o <= ( others => '0' );
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cy_o <= cy_i;
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cy_o((DWIDTH-1)/4) <= dcml_cy_i;
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ov_o <= ov_i;
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else
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result_a_o <= ( others => '0' );
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result_b_o <= ( others => '0' );
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cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
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ov_o <= '0';
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end if;
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when DIV_ACC_RAM =>
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if (C_IMPL_DIV /= 0) then
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result_a_o <= qutnt_i;
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result_b_o <= rmndr_i;
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cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
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if ram_data_i = conv_std_logic_vector(0,DWIDTH) then
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ov_o <= '1';
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else
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ov_o <= '0';
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end if;
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else
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result_a_o <= ( others => '0' );
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result_b_o <= ( others => '0' );
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cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
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ov_o <= '0';
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end if;
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when MUL_ACC_RAM =>
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if (C_IMPL_MUL /= 0) then
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result_a_o <= product_i(DWIDTH-1 downto 0);
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result_b_o <= product_i(DWIDTH*2-1 downto DWIDTH);
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cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
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if product_i(DWIDTH*2-1 downto DWIDTH)
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= conv_std_logic_vector(0, DWIDTH) then
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ov_o <= '0';
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else
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ov_o <= '1';
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end if;
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else
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result_a_o <= ( others => '0' );
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result_b_o <= ( others => '0' );
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cy_o <= conv_std_logic_vector(0,(DWIDTH-1)/4+1);
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ov_o <= '0';
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end if;
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when SUB_ACC_RAM | SUB_ACC_ROM | ADD_ACC_RAM | ADD_ACC_ROM |
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ADDC_ACC_RAM | ADDC_ACC_ROM =>
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result_a_o <= addsub_rslt_i;
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result_b_o <= ( others => '0' );
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cy_o <= addsub_cy_i;
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ov_o <= addsub_ov_i;
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when INC_ACC | INC_RAM | DEC_ACC | DEC_RAM =>
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result_a_o <= addsub_rslt_i;
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result_b_o <= ( others => '0' );
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cy_o <= cy_i;
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ov_o <= addsub_ov_i;
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when others =>
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result_a_o <= result_i;
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result_b_o <= ( others => '0' );
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cy_o <= new_cy_i;
|
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ov_o <= ov_i;
|
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end case;
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end process p_rslt_mux;
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|
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end rtl;
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